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At IEDM in December, there was a full-day course looking at the options for transistors and interconnect for the 5nm node. The academics opened the show with Mark Lundstrom presenting on behalf of a team from Purdue, MIT, and NYU on Device Options and Tradeoffs. Then it was IBM's turn with Bruce Doris on FEOL Integration Issues, and Takeshi Nogami on BEOL Process Challenges. Then back to academia with Krishna Saraswat of Stanford on Emerging Interconnect Technologies. These four presentations split nicely into an academic and industry position on future devices (FEOL), and an academic and industry position on interconnect (BEOL).
Mark Lundstrom started by pointing out that for silicon we have to live with the subthreshold slope being at least 60mV/decade. We can't build a better device (out of silicon) by improving the subthreshold slope, and so at 5nm the the leakage current goes through the roof however much we play around with voltages and thresholds. Like in The Matrix, Mark proposed a red solution and a blue solution. The red solution is to increase the on-current so that we can get the same drive at a lower voltage.The blue option is to find a way to get the subthreshold slope below 60mV/decade, which means using something other than silicon, so then we can lower the voltages without the leakage killing us.
The rest of his talk was modeling a large number of possible future technologies. You can see the names of some on the diagram above showing the two options. I'm not going to go into any of them in detail since, while they may be interesting from a research point of view, they all struggle with the same issues, in particular the difficulty of achieving the desired on-current at a voltage that doesn't give you an undesirable off-current.
Bruce's conclusion was that no device that is distinctly superior to silicon has been identified.
But there is a bigger issue. Bruce Doris came on next and dismissed them all as not ready. He pointed out that it takes over ten years for a technology to go from the research lab to volume production, often more like fifteen. FinFETs, for example, were first being talked about in the late 1990s (Chenming Hu's paper is dated 1999). So any of the technologies Mark discussed are not going to be ready for production until 2025 or maybe 2030, too late for 5nm. So his view is that, at 5nm, it will be some sort of FinFET (possibly gate-all-round silicon nanowire, but that is still a very similar type of device).
However, in order to get the density up we will also need self-aligned-contacts, since otherwise the contacted poly pitch (CPP) is simply too large. There will need to be a lot more strain engineering and the incorporation of III/V materials. If we go to nanowires, since a single wire carries less current than the fin it would replace, that is not a competive. So if we go that way we will need multiple stacked wires (or perhaps vertical wires but nobody really knows how to do that yet). Nanowires still need CPP to be reduced too.
Next up was Takeshi Nogami, who gave a worldwind tour of all sorts of potential interconnect technologies. But in the end his conclusion was that we need to incrementally improve what we have got, namely:
Krishna Saraswat worried about how we can improve interconnect performance. Again he had a whirlwind tour of possibilities:
So after a day drinking from a firehose on all these possible future technologies, it looks like the future is going to be very like the present: