Coming up in the beginning of December is the 65th International Electron Devices Meeting (IEDM). The slightly strange name comes about because this is the 65th, meaning it started in the fifties, long before integrated circuits had been invented. Indeed, even transistors were obscure devices pushed off into a couple of sessions at the end. Vacuum tubes were the primary "electron devices" of the era.

This year's IEDM will once again be held at the San Francisco Hilton from December 7 to 11. The conference proper is Monday to Wednesday, with tutorials and short courses at the weekend. The overall theme of this year's conference is Innovative Devices for an Era of Connected Intelligence. You can watch the publicity video for the conference:

Saturday, December 7

Saturday is tutorial day. There are two tutorial slots, with three tutorials in parallel in each slot.

At 2:45pm, the first group of tutorials is:

• Oxide Semiconductors and Applications taught by Hideo Hosono of Tokyo Institute of Technology
• In-memory Computing for AI taught by Abu Sebastian of IBM Research, Zurich
• Magnetic Field Sensors taught by Keith Green of Texas Instruments

At 4:15pm (after a break, I assume), the second group of tutorials is:

• Cryogenic MOSFET Modeling taught by Christian Enz of École polytechnique fédérale de Lausanne (EPFL)
• Ferroelectric Memories and Beyond taught by Johannes Műller of GLOBALFOUNDRIES
• Sequential Integration taught by Perrine Batude of LETI

Sunday, December 8

Sunday is the day of the short courses. There are always two, one on digital logic, and one on memory. They run in parallel from 9:00am to 5:30pm so it is only possible to attend one.

First, the digital one this year is called Technology Scaling in the EUV Era and Beyond:

• Future of Computing: From Core to Edge Computing by Karim Arabi of Atlazo
• Device Technology for 3nm and Beyond by Jin Cai of TSMC
• EUV Lithography Technology by Ho Chul Kim of Samsung
• Design Technology Co-Optimization for 3nm and Beyond by Lars Liebmann of TEL
• Novel Interconnect Techniques for Advanced Devices Beyond 3nm Technologies by Chris Wilson of imec
• Ultra-Low Power Devices for Advanced Signal Processing Architecture by Arokia Nathan of Cambridge Touch Technologies, University of Cambridge

The memory course is titled Technologies for Memory-Centric Computing:

• Memory Devices and Selectors for High-Density Memory Technologies by Alessandro Calderoni of Micron Technology
• 3D-Stacked DRAM Technology and Function-in-Memory Solution by Kyomin Sohn of Samsung
• Novel Memory Technologies for Advanced Nodes by Oleg Golonzka of Intel
• Emerging Technologies for Memory-Centric and Low Power Architectures by Edith Beigne of Facebook
• Towards Memory-Centric Autonomous Systems: A Technology and Device Perspective by Arijit Raychowdhury of Georgia Institute of Technology
• 3D NAND: Challenges and Potentials by Jian Chen of Western Digital

Monday, December 9 - AM

The conference proper opens with Session 1, the plenary session. This always starts with awards and then there are three plenary keynotes:

• Process and Packaging Innovations for Moore’s Law Continuation and Beyond by Robert Chau, Senior Fellow at Intel Corporation
• Continued Scaling in Semiconductor Manufacturing Enabled by Advances in Lithography by Martin van den Brink, President and CTO at ASML
• Future of Non-Volatile Memory: From Storage to Computing by K. Ishimaru of Institute of Memory Technology R&D, Kioxia Corporation (you might not recognize the name, this is what used to be Toshiba Memory)

At the end of the day, there will be a reception at 6:30pm.

Monday, December 9 - PM to Wednesday, December 11 - PM

For the rest of the conference there are a large number of parallel sessions. In among them are some special focus sessions, primarily with invited papers. Look out for:

• Emerging AI Hardware Technologies
• Human Machine Interface
• Quantum Computing Infrastructure
• Reliability and Security for Circuits and Systems

On Tuesday evening, from 8:00pm to 10:00pm, there will be a panel session Rest in Peace Moore's Law, Long Live Artificial Intelligence.

As always, IEDM accepts some significant late papers, typically major manufacturers announcing next-generation processes of one sort or another. The three that IEDM have already pre-announced are:

Paper #36.7, 5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility
Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing
Applications, G. Yeap et al., TSMC

TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channel mobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in high-speed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20.

Paper #29.7, 300mm Heterogeneous 3D Integration of Record Performance Layer Transfer
Germanium PMOS with Silicon NMOS for Low-Power, High-Performance Logic Applications, W. Rachmady
et al., Intel.

CMOS technology requires both NMOS and PMOS devices, but the performance of PMOS lags NMOS, a mismatch which must be addressed in order to wring every last bit of performance and energy efficiency from future chips. One way to do that is to build PMOS devices with higher-mobility channels than their NMOS counterparts, but because these are built from materials other than silicon (Si) which require different processing, it is challenging to build one type without damaging the other. Intel researchers got around this with a 3D sequential stacking architecture. They first built Si FinFET NMOS transistors on a silicon wafer. On a separate Si wafer they fabricated a single-crystalline Ge film for use as a buffer layer. They flipped the second wafer, bonded it to the first, annealed them both to produce a void-free interface, cleaved the second wafer away except for the Ge layer, and then built gate-all-around (GAA) Ge-channel PMOS devices on top of it. There was no performance degradation in the underlying NMOS devices, and in an inverter test circuit the PMOS devices demonstrated the best Ion-Ioff performance ever reported for Ge-channel PMOS transistors (Ion=497 µA/µm and Ioff=8nA/µm at 0.5V). The researchers say these results show that heterogeneous 3D integration is promising for CMOS logic in highly scaled technology nodes.

Paper #2.7, 22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability and Magnetic Immunity and with Performance and Shielding Options, W. Gallagher et al., TSMC

Many electronics applications require fast nonvolatile memory (NVM), but embedded flash, the current dominant technology, is becoming too complex and expensive to scale much beyond 28nm. A type of embedded NVM known as STTMRAM has received a great deal of attention. STT-MRAM uses magnetic tunnel junctions (MTJs) to store data in magnetic fields rather than as electric charge, but this ability decreases as
temperature increases. That makes STT-MRAM both challenging to build – it is fabricated in a chip’s interconnect and must survive high-temperature solder reflow – and also to use in applications such as automotive, where thermal specifications are demanding and the ability to resist outside magnetic fields is critical. TSMC will describe a versatile 22nm STT-MRAM technology that operates over a temperature range of -40ºC to 150ºC and retains data through six solder reflow cycles. It demonstrated a 10-year magnetic field immunity of >1100 Oe at 25ºC at a 1ppm error rate, and <1ppm when in a shield-in-package configuration. The researchers say that by trading off some of the reflow capability and using smaller MTJs, even higher performance can be achieved (e.g., 6ns read times/30ns write times), making them appealing for artificial intelligence inference engines.

Details

Full details, including a link for registration, are on the IEDM website.

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