IEDM: All About Interconnect

The first week of December means it is IEDM, the International Electron Devices Meeting. This meeting pre-dates the integrated circuit and nearly pre-dates the transistor, so "electron devices" had a different meaning. In recent decades, the focus has been on the "devices" in integrated circuits, a mixture of next-generation devices for continuing to advance semiconductor scaling (such as gate-all-around, GAA), and unusual devices that have some useful characteristic (like high-bandgap GaN, or tunneling TFETs, for example). But if I had to pick a trend for this year's IEDM it would be the importance of interconnect.

One warning I remember from IEDM a couple of years ago was that a new technology takes ten years to go from research (an IEDM paper, say) to high-volume manufacturing (HVM). This was in the context of a couple of sessions on next-generation transistors and next-generation interconnect. After the academics had talked about all sorts of esoteric technologies, the industry guys came on and said, basically, that there is no time for something really new, so next-generation transistors will be something very like FinFETs (GAA for example) and next-generation interconnect would be a damascene process using copper, or perhaps a different metal like cobalt.

So papers at IEDM actually fall into two rough groups, incremental development of technologies we already use which have some chance to be adopted in the short-term, and wild ideas, which are ten years out from appearing in an electronic device in your pocket.

The IEDM Video

This year, IEDM made a pre-conference video about microelectronics, presumably to encourage attendance. I thought it was really good, only going a bit hyperbolic on silicon brains (and the "beautiful" San Francisco Hilton, a hotel to which the word "beautiful" has never been applied by anyone before).

Samsung

Samsung's ES Jung kicked off the plenary session called The 4th Industrial Revolution and Foundry: Challenges and Opportunities. Today he is Samsung's VP of Foundry, but in the past, he ran semiconductor R&D. For sure he knows lots about electron devices.

I have seen a lot of presentations about the "fourth industrial revolution" recently, and it is interesting to see what presenters pick for the previous three. There is pretty much universal agreement on the first industrial revolution, which started in England in the mid 18th century, but ES went for 1804, with the steam locomotive as the archetypal example. Next was mass production in 1913 with the conveyor belt (so roughly 100 years later). The third was electronics where he picked 1971 with the personal computer as his example (but with a more realistic 1971 image of a mainframe). Now, in the 2010s, we have cyber physical systems. The first industrial revolution lasted 100 years, the second 50 years, and the third 30 years. The fourth has now started.

No surprise that semiconductors are the key driver. A smart phone contains 80 different semiconductors of 50 different kinds. A smart car is predicted to contain 6,000 semiconductors.

Since Samsung is one of only two companies that provide leading-edge foundry at 7nm and below, he emphasized the importance of speed, power, area, and density for the future. The big missing graph, to me, is cost. The cost of manufacturing a million transistors is somewhere between staying flat and rising. The cost of doing a design in an advanced node is getting so complex that people are forecasting billion dollar budgets. I don't think that is true for most SoCs. For example, at the recent Linley Conference, Google's Cliff Young talked about the four versions of the TPU chips that his group has created over the last three years, and the scalable systems built using them. While Google can afford billion-dollar budgets, and maybe you can get there if you add in all their investment on AI in general, I think they are designing their chips (admittedly not yet in 7nm) for a lot less. See my post Inside Google's TPU for more details.

At 7nm, EUV is finally being introduced for volume manufacturing. ES said that they now have 250W source power, enabled by pre-pulse (two lasers) and active isolation. He said they have mask qualification systems enabled by EUV source and optics for metrology. Pellicles are not ready yet. There was a lot more technical detail about EUV in the Sunday short course (from ASML's Anthony Yen) which I'll cover in another post.

As it happens, Samsung foundry marketing's Bob Spear was recently interviewed on video by ChipEstimateTV's Sean O'Kane about EUV introduction.

TUV Dresden

The second plenary presentation was by Gerhard Fettweiss of TUV Dresden. To be honest, I wasn't expecting much since the abstract in the agenda was written in the kind of bureaucratic English that I associate with the European Union, that always looks like those anecdotes where you translate perfectly good English into a foreign language and back:

We pursue an approach that connects all layers from new materials to new system design (vertical) as well as across our Research Routes (horizontal) and ensure coherence through adequate measures. cfaed is centered at one location which, combined with our unique approach, places it above the highly funded Competitive Landscape.

cfaed isn't a misprint, it's the fashionably all-lowercase acronym for the Center For Advancing Electronics Dresden. Gerhard talked about a lot of different technologies, so I'll just pick a couple.

As it happened, the last question to ES in the first presentation was about what comes after 5G, and he wasn't sure but that it would be 6G. Gerhard's first slide was about 6G. He said that the 5G standard was rushed by about two years so that it would be ready for the Tokyo Olympics in 2020. As a result, many key requirements were not considered. It is more like a new LTE radio with massive MIMO (multiple antenna) support. In fact, he pointed out, the standards tend to be like that: first we had 1G analog telephony that became digital with 2G (GSM in most of the world). It was all about voice. 3G was meant to be about video telephony but it was way too expensive for that, but video became a reality with 4G (the current standard). 5G is the entry point for the tactile internet but it will be 6G that makes it really happen. Many 5G applications result from wanting to use the cellular network to control real and virtual objects (such as automated driving and augmented reality).

The official view of 5G has three facets (each with its own acronym, of course):

• eMBB extreme mobile broadband
• URLLC ultra-reliable low-latency communications
• mMTC massive machine-type communications

Gerhard thinks the data rates are just too low:

In 2002 I said to Eric [CTO of Vodaphone who is a major funder of cfaed] that data rates will double rapidly, 10X increase every 5 years. It was a big challenge to convince him and anyone else. But now we are looking towards terabits. Who needs a terabit wireless? I sat sown with the AR/VR teams at Google, Facebook, and Disney. You need at least 100Gb/s to feed a nice pair of goggles without it being pixely, and with very low latency to stop it making you sick. Today that needs a cable. So we need to get across the valley to terabit wireless.

Next, 5G latency (5ms) is just too high:

If we move something in front of our face, our visual system wants to see reactions in the 1ms range of values. But todays internet is more like 100ms. 5G can do real-time audio, 5ms is enough, but not real-time video yet (needs 1ms). We will move to a wirless infrastructure for remote control of robots, cars, and drones. That also requires 1ms latency, or you can't do things like traction control.

And power is too high:

The killer is the ADC [analog to digital converter]. We need 12-bit resolution and a high sampling rate, so a lot of power. We want a reconstruction where the quantization noise is less than the thermal noise, so as good as perfect as we can achieve, but we can't do that any more. QAM [quadrature amplitude modulation] and all the stuff we've learned may have to go. There seems to be significant benefit from oversampling in terms of achievable rate which we demoed ain September. This is zero-crossing modulation. So we can build this but we will have to reinvent how to build transmission systems.

In the questions, someone asked Gerhard about unlicensed spectrum (such as WiFi). Gerhard said that it will be important but you can't have service guarantees with unlicensed, which is important for things like traffic lights. That pointed out another weakness that 5G did not consider, interference from one smart factory next to another, or a kid with a high-gain antenna pointing it at the central unit. "All this was forgotten by the 5G standards, but the military worries about this jammer-free vision."

IBM

The final plenary presentation was by Jeff Welser of IBM Future Computing Hardware for AI. He started with a sort of tutorial on neural nets and how they can be optimized. I'll simply point you at my post HOT CHIPS Tutorial: On-Device Inference.

His summary of where we are is that specialized AI finally works for applications like language translation, speech transcription, understanding, object detection, and so on. This is what he calls "narrow AI". We are moving toward "broad AI" where it is multi-task multi-domain, explainable, and distributed. But he feels that "general AI" is 2050 and beyond, where we have cross-domain learning and reasoning, and broad autonomy.

Currently, we rely on pure computational horsepower. It is a “happy coincidence that GPUs are good at doing neural networks too, both need lots of matrix multiplication”. But the power is a problem. Imagenet-22K with resnet-101 takes 2564 GPUs 7 hours...but 450 kWh. He sees three different tracks to make this more efficient:

1. Better GPUs.
2. Emerging technology with more approximate values, perhaps going back to analog.
3. Even further out, quantum computing may be applicable.

In the emerging technology area, one attractive approach is to:

...eliminate the Von Neumann bottleneck. Map the neural networks to analog cross point arrays. Use non-volatile memory materials in the array crosspoints to store the weights. Each point is a variable resistor. We can really get the advantage that the weight is in the memory, and not being moved in and out of external weight memory. Our preliminary results are 100X faster and 280X more energy efficient.

IBM has built the TrueNorth chip for low-power inferencing, with 4,096 neurosynaptic cores and an on-chip network for a total of over 1 million programmable neurons and over 256 million configurable low-precision synapses. The chips can be tiled into bigger systems.

Quantum computing is very attractive for some things. In classical computing, there is a one-to-one relationship between the number of transistors and processing power, whereas quantum computing goes up as 2^N, so it is exponential when you add another qubit. This comes about from the superposition and entanglement, where the entangled qubits cannot be described independently of each other, and so you get a sort of massive parallelism. In the current IBM solution (which anyone can use on the cloud) they use microwave signals to control the chip, with Josephson junctions being used a non-linear inductor. Superconducting microwave resonators are used to read out the qubit states. The current state of the art is to have the chip at 15 milli-Kelvins, much colder than space, and keep the qubits entangled for 100us.

Jeff said that the things quantum computing is really good for but classical is not for chemistry, portfolio optimization, machine learning, and some other areas. But factoring large numbers, one of the things on which internet security depends, is not one of them since we need millions of stable qubits, which is decades away. Plus, other forms of cryptography, like lattice cryptography, don't map onto quantum.

But quantum computing applied to AI promises to solve problems we now simply cannot attempt, even on the leadership systems like the Summit supercomputer.

Interconnect

As always, the Sunday of IEDM consists of two short courses run in parallel, one on logic and one on memory. Apparently, this was the first year that more people attended the memory one. I went to the logic one that was titled Scaling Survival Guide in the More-Than-Moore Era. It covered everything from EUV, to scaling boosters and DTCO, to packaging. I'll cover some of that in a future post.

I said that a theme of this year's IEDM was interconnect. One of the special sessions on the first day was a series of invited papers on new interconnect materials. I'll cover that in a future post. Get used to hearing more about ruthenium, iridium, and molybdenum.

This year IEDM overlapped with the RISC-V Summit (they don't next year) so I wasn't able to attend the last couple of days, in particular, the presentation of Samsung's 3nm process. But I do have the paper, so I'll pull the highlights (and some images) from that.

Talking of next year's IEDM, if you want to put it on your calendar, it will be at the same location on December 9th to 11th, 2019 for the conference proper, presumably with tutorials on 7th and short courses on 8th.

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