Use Your Imagination to Get Smaller, Faster Chips

At the recent CadenceLIVE Americas, Nick Loebner of Imagination Technologies presented Delivering Best PPA on PowerVR GPUs Using Genus/Innovus Digital Implementation System. You probably already know that Imagination Technologies license GPU IP. It is based in the UK at Kings Langley, about an hour's drive from Arm in Cambridge...must be something in the water in the South East of England.

The company was founded in 1985 as VideoLogic and worked closely with VLSI Technology in those early days. They built actual chips for graphics and audio (and Sega game consoles). I don't think the idea of IP licensing had even been invented by then. In 1999, it focused on IP and changed its name. It was years later that I put two and two together and realized that the chip company that we'd dealt with in the '80s and '90s called VideoLogic and the IP licensing company called Imagination Technologies were one and the same.

One challenge all IP licensing companies have is that how good its product appears to its customers depends not just on the IP it creates, but how good the implementation tools can handle the design. That, in turn, means creating a reference flow that its licensees can use successfully. It can't be too weird or complicated either, since Imagination's licensees need to be able to adopt and run it successfully.

Innovus Reference Flow

Since Cadence's digital full flow had been updated with iSpatial technology that unified synthesis and physical design, they decided to see just how good a result they could get. They found that with Genus/Innovus they got 20% better results than they did with their previous flow. The table below shows some of the results for a 1GHz clock-rate reference flow.

These results were obtained with adoption of iSpatial and early clock flow, high effort synthesis, and extreme PnR flow with standard CCOpt. They also found a very tight correlation between iSpatial (after synthesis) and Innovus (after physical design). About 80% of paths were within 2% and 90% within 3%.

They wondered if they could do better, and so they went for a 10% performance push to 1.1GHz.

As you can see, they made it. All the slacks are very close to zero even at a 1.1GHz clock rate.

One thing that they noticed was that the densities were around 67-69%. So they decided to have a 10% area push (keeping the clock at 1.1GHz) and see if they could get Innovus to successfully route at a higher density and thus reduce the area by 10%. Of course, for the licensee, reduced area translates directly into reduced manufacturing cost. And since GPUs are big and tend to occupy a significant fraction of the die, this can be a big reduction in the overall cost of the SoC. Or as Rob put it:

Significantly improves performance density for all those aiming to drive down costs

They just did one block but as you can see they pushed the density up to over 75%. "It was cleanly routable at this utilization", Rob said.

Overall Performance

Rob's graph above shows how PowerVR with the Cadence digital full flow delivers not only the highest performing GPUs but also the most power efficient. It seems that Imagination can operate at higher frequencies while remaining competitive on power, meaning that customers have a very broad DVFS (dynamic voltage and frequency scaling) suitable for a broad range of applications.

Conclusions

Greg's final conclusion bullets:

• Using Genus and Innovus iSpatial and PowerVR, we were able to extend our competitiveness by 20% and achieve greater than performance density improvement within a 2W sustained power budget.
• Working in close collaboration with Cadence, we are able to offer our mutual customers best-in-class PPA on leading technology nodes
• Genus iSpatial Synthesis offers tight correlation (within 3%) and critical path correlation to post-route results in Innovus Implementation
• All results were achieved without excessive customizations to the Common UI reference flows

Learn More

See the product page Digital Design and Signoff.

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