Get email delivery of the Cadence blog featured here
I recently visited imec. For an overview of my day, see my earlier post If It's Tuesday This Must Be Belgium. My First Visit to imec. One of the things that imec does is to take the funnel of potential process developments and get some industry consensus on what next-generation processes will look like. This is important, since the equipment manufacturers and the material suppliers, as well as EDA developers like Cadence, need a roadmap to know what needs to be supported.
As I said in my earlier post, imec is neutral territory for everyone to cooperate out in the pre-competitive era. A few years ago, that was 5nm, but now 5nm is being installed in production fabs, and the focus is now on 3nm and beyond. Cadence and imec recently taped-out a testchip to validate some aspects of manufacturability at that node.
I was given a presentation by Diederik Verkest on how they see the scaling landscape for logic. The big picture is that direct pitch scaling of the process is not possible. Instead, design technology co-optimization (DTCO) is needed. This allows area scaling to continue on the 50% per node heartbeat, but with relaxed pitch scaling. The above chart is the master roadmap, summarizing a huge amount of data. You can read off critical pitches, lithography technology, estimated dates, and more.
First, a word about process naming. Imec names processes generations iN8, iN7, iN5 etc. The foundries use more aggressive "marketing" numbers, and call roughly equivalent processes, 7nm, 5nm, and 3nm. Intel is more conservative and uses numbers closer to the imec numbers. To be honest, I don't know why they don't just give up and use the same process names as the foundries, since they burn a lot of energy explaining how their 10nm process is what the foundries call 7nm, if you look at all the critical pitches, and still investors don't really understand it. There is really nothing on a 10/7nm process that is 10/7nm anyway (the pitches are around 56nm for the CPP and 40nm for the metal pitch). However, you will still see people assuming that the gates "are 14nm across" in a 14nm process.
Also, a word about lithography, since it is all in transition. When we first went to double patterning, we used LELE, for litho-etch-litho-etch. This creates the two "colors" of the layout with two separate masks that are not self-aligned. When we needed tighter control, we went to SADP, self-aligned double patterning. A sacrificial mandrel is laid down, then spacers built against the mandrel, and then the mandrel is removed. The spacers are used as the masks for filling with copper (or whatever the material is), then they too are removed. SAQP, self-aligned quad-patterning, does a second round of doubling. After the first mandrel is removed, the spacers left are used as mandrels to form a second set of sidewall spacers at half the pitch. In second generation 7nm processes from the foundries, EUV (extreme-ultra-violet) lithography is being introduced, using 13.5nm wavelength light and going back to single patterning. However, for 3nm even EUV will need some double patterning. Later that day, I got a presentation from Kurt Ronse on EUV readiness, and I'll cover that in a separate post. For this post, just assume that it will be ready for second-generation 7nm, and all 5nm or later processes.
What these scaling challenges mean in practice is that some tracks need to be cut out of the standard cell libraries. It is not possible to just remove tracks, or it would have been done already. Scaling boosters in the process are required to make this possible. Similarly, scaling boosters might be required to shrink the SRAM cell height.
Looking at the transistors, the challenges are:
With interconnect, there are problems just scaling copper (Cu) interconnect. The resistance goes up exponentially for narrow lines. Copper requires a barrier but the barrier (liner for contacts) is a fixed thickness, leaving less and less room for copper in the narrow wires and contacts (plus, at the bottom of every contact, the current has to flow through the bottom of the liner). Even though, as a metal, ruthenium (Ru) is higher resistance than copper, it doesn't require a barrier and thus is a potential source of relief since Ru is lower resistance than Cu with a liner.
For 3nm, the key scaling boosters look like they are buried power rail, and complementary FET. This allows further shrinking of the standard cell to just 3 tracks, the ultimate in track height scaling, and using double-height cells for the most complex storage elements, adders, and so on. Buried power rail means that the power is laid down before the transistors are created, as part of the FEOL. Complementary FET, or CFET, has the NFET and PFET stacked vertically with a common gate. One of the challenges at 3nm, with such small cells, is to router access to the ports. However, it turns out that burying the power rails frees up a lot of resource and so 3 track cells with buried power are easier to route than 4.5 track cells without.
To get the cell size down, it is necessary to go to a single fin. However, that requires a larger fin height than the 30nm used for a two-fin cell. But that turns out to be limited to about 50nm. Beyond that height, the parasitic device capacitance becomes large and increasing the fin height actually reduces the performance.
Instead, going to lateral nanonsheets (LNS) looks like it needs less aggressive performance boosters as a result. LNS provide a better Weff for the same footprint area as a single 50nm fin, and with the same total height.
A word about manufacturing. The lateral nanosheets are implemented on the wafer as the first process steps. An alternating sandwich of channels and spacer is laid down onto the bare wafer, across the whole wafer. Since this does not require a lot of lithography steps, it is relatively cheap. Later, lithography is used to define the actual nanosheet gate stacks, and insert the replacement gate. But my first thought, when I saw nanosheets, was wrong. They are not built up with dozens of mask steps, which would be prohibitively expensive.
Traditional device scaling continues but dimensional scaling impacts performance too. Fundamental new devices such as carbon nanotubes or 3D materials are still far from maturity. I have heard other people say that it takes 10 years for a device to go from the lab to high volume manufacturing. So we are "stuck" with something close to what we have today, with complex device performance boosters been necessary, but providing diminishing returns.
The first set of scaling boosters, used with DTCO, reduce logic and SRAM cell area without relying on device/wire dimensional scaling. The minimal track height is 3 metal pitches, using buried power rails and CFETs. SRAM cell height scaling saturates at the equivalent of 5 fin pitches.
System Technology Co-Optimization (STCO) complements all this, and optimizes invisible SoC functions such as power delivery. Ultimately, to speed up software, requires new computing paradigms supported by technology such as machine learning, compute-in-memory, and new fabrics.
So there have been three eras. In the first, the focus was to scale the devices and wires. In the second, the focus was reducing the size of basic logic cells (and the SRAM cell). In the future, the focus has to move to scaling entire sub-system functions.
Areas that imec is investigating in the STCO area that look promising are:
IEDM, the International Electron Devices Meeting, is the main conference for new devices and processes. It will take place December 1st to 5th in the San Francisco Union Square Hilton. The theme this year is Device Breakthroughs from Quantum to 5G and Beyond. The reason that I'm dropping this paragraph in here is that the call for papers has just opened, and the deadline for submissions is August 1st. Details are on the IEDM website. I will be at IEDM in December and you can expect to see several posts here on Breakfast Bytes covering the biggest announcements.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.