Innovus Mixed Placer

It has been a dream for a long time to have a fully automated mixed placer that does a good job. In fact all physical design systems have had the capability for a long time, but designers were reluctant to use them on simple designs. When there were just a few blocks, designers would typically place them manually around the edge of the design, leaving a sea for placing and routing standard cells in the center. But two things have happened to change the situation.

The first is that the number of blocks, especially memories and register files. has gone up so that it is time-consuming to use manual methods, and inceasingly hard to come up with a "good" floorplan.

The second is that the placement technology in Innovus has improved.

Broadcom Case Study

To give you an idea how much, at CDNLive 2019, Jack Benzel of Broadcom presented Concurrent Placement of Macros and Std Cells with the Mixed Placer. Have They Finally Done It? (his Powerpoint is still available at the link).

To give you an idea of the complexity of a modern design, these images are from Jack's presentation. At the top is the manual floorplan, which took over two engineer days and a week of runtime. At the bottom, the mixed place took less than four hours, and came up with a better placement.

Cadence recently produced a white paper Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation which goes into more detail.

The Traditional Approach and Problems with It

Everything is about data these days. You've probably seen facts like 90% of the data ever generated was created in the last couple of years. Or that a jet aircraft produces a terabyte of data on an intercontinental flight. So datacenters and edge devices need to transmit, receive, and analyze large amounts of data. To handle the capacity and efficient movement of this data, new data and memory-centric design architectures are gaining popularity in the world of IC design. These new age ICs are required to capture, store, and analyze data as part of the artificial intelligence systems’ storage and inferencing cycle. Since large amounts of data need to be moved from one place to another, new design architectures see increased on-chip storage elements like SRAMs and register files. As a result, these design layouts have a much higher ratio of memory to logic elements than traditional compute-centric ICs designed with the basic Von Neuman architecture. This is only expected to grow, as you can see in the diagram below. The green is memory.

The historical approach has been a very manual method. Macros are normally placed around the chip periphery while considering connections to fixed cells and I/Os, leaving a continuous space (area) in the middle for standard cell placement, as in the diagram. Macros are later moved and placed correctly according to the desired orientation to minimize the distance between the pin connections. Additional floorplanning steps include reserving space for power grids, adding macro halos, and adding placement and routing blockages to avoid notches or thin channels to guide the placement of standard cells.

With only a few macros, this has worked. However, one major problem with this approach is when the macros are confined to the sides of the available area, longer wirelengths are forced The detailed legalized placement of the standard cells is not known at that time, so based on the assumptions, the placement may not be optimal for timing and congestion as well. With manual adjustments to the macro locations, some of these can be improved with multiple trial-and-error iterations, but it is a manual, error-prone process causing delays in floorplan delivery.

A New Approach: Mixed Placement

If macros are not bound by the limitation to be anchored to the four sides of the available area and are instead allowed to “float”, there is more flexibility for the placement algorithms to find an optimal location to a multi-objective optimization problem. But with hundreds or even thousands of macros, this is simply not feasible to handle manually.

The mixed placement technology, GigaPlace XL within the Innovus Implementation System, is an extension of the powerful multi-objective standard cell placement GigaPlace engine. The GigaPlace XL engine can handle the placement of these macros together with the standard cells and I/Os in the same step, concurrently. In reality, macro placement is a combinatorial problem, while standard cell placement is a numerical one. The breakthrough achieved by the GigaPlace XL engine inside Innovus Implementation is that, with its solver-based placement technology, it can solve continuous optimization and combinatorial optimization simultaneously.

This offers two key benefits:

• Standard cells can be placed on all four sides of the macros, resulting in more resources for timing and wirelength optimization, which leads to improved timing, area, and power.
• A slack-aware numerical solver looks at standard cell delays while doing a macro placement, reducing the approximation involved in combinatorial trial-and-error analysis methods, resulting in fewer iterations while delivering a feasible, working floorplan.

The diagram above compares the traditional manual flow with a lot of iteration on the left. The new mixed placement flow is on the right. Flexible flows are available based on user preference so a user can start with or without a reference floorplan. The flow involves basic modeling of the power grid density, cleaning up floorplan objects, setting constraints for macro placement, and then running the GigaPlace XL engine to achieve concurrent macro and standard cell placement. After the initial placement based on solving the multiple objectives, legalization and macro refinement steps follow, along with physical cell insertion and actual power routing. After this step, standard cells can go through an incremental flow for legal placement followed by pre-cts optimization. 

And the table below shows the improvement for a test example. The mixed placement does better for timing (total negative slack, worst negative slack, failure endpoint), lower power, shorter wirelength, fewer DRCs, and so on.

Learn More

There is lots more detail in the white paper if you want to dig deeper. Here's the link again.

We also have a brief video Better PPA with Innovus Mixed Placer Technology — Gigaplace XL:

I'll give Broadcom's Jack Benzel the final word. Remember, his CDNLive presentation title was Concurrent Placement of Macros and Std Cells with the Mixed Placer. Have They Finally Done It? and his last slide just had one sentence:

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