Get email delivery of the Cadence blog featured here
For most chips, the automatic routing in Innovus—NanoRoute—works well. But there are certain styles of chips that are more challenging for a grid-based router to do clean structured routing.
Grid-based routing has some limitations for this sort of design and a shape-based or space-based router is normally used. The 16.1 release of Innovus early last year introduced structured routing in the form of the Innovus High-Frequency Router. This router is based on the NanoRoute infrastructure and can do structured routing in the digital P&R environment. The automated solution then fills in everything else. Now, in the 16.2 release, there is a fully integrated bus routing solution, built around the idea of a busSinkGroup.
The 50,000' view of this capability is that it allows floorplanning of buses (typically wide and long) at the top level, allows buses to be planned as a whole, takes care of all aspects of the buses to be captured for implementation and routes the buses in a structured way during the detailed routing step. These capabilities add a much easier interface to the Innovus High-Frequency Router, along with some incremental capabilities.
Specialized analog routing has lots of specialized functions so that the analog behaves as desired. But what are known as big-D small-A designs requires some of the same capabilities. These are designs that are largely digital but also have an analog aspect too. Very high-frequency designs also share some of these aspects, since at high frequency the digital illusion starts to break down and some of the signals need to be treated more like analog signals. The functions that are supported by the integrated bus routing solution are:
These features can also be used in two ways:
Another issue is long signals. In the simplest case, these require buffering, but this must be done in a controlled way so the bus timing remains correct. One way to do this cleanly is distance-based buffer insertion, where buffers are inserted on every signal at regular spacing.
In the case of the longest signals of all, buses need not just buffering, but also register insertion, so that the signals can make it all the way across the chip, taking several clock cycles to do so. These are known as pipeline flops. Because adding registers changes the sequential behavior of the circuit, this requires interaction with synthesis to add them and fix up timing before the physical design is completed. The diagram below shows details of the flow.
At corners, where buses need to make a right-angle turn, river-routing the bus is often inadequate (although it is supported) because there is too much timing difference between the signals on the inside and the outside of the curve. Instead, an equal wire-length turn is required, so that skew is minimized. See the picture to the right.
In summary, these features allow buses to be planned at the top level and pushed down into the hierarchy. Buses can be planned as a single object for overall planning, specifying buffering, pipeline flops, shielding, and other analog style constraints. By handling the most critical large long-distance buses first, higher performance can be achieved that would be possible using the grid-based routing alone, and design closure can be achieved earlier.