Intel 10nm

At IEDM last month, Intel announced details of their 10nm process. Later the same morning, they also gave details on a 22nm process, 22FFL, which is a second generation 22nm process (their first FinFET process was also 22nm) targeted at mobile and RF development.

Since Intel had already discussed some of what would be in their upcoming 10nm process, there were no major surprises but there were a lot of details that I've not seen before.

10nm

Here is the one paragraph summary. The Intel 10nm process is their 3rd generation FinFET process. All channels are undoped. It has 3 layers of SAQP (the first time in logic). It is the 5th generation of HKMG with 3-6 work function metal electrodes. It is the 7th generation of strained silicon, and the 2nd generation of low-K spacer. They continue to use a self-aligned trench contact with cobalt. Cell boundary isolation has been optimized so that it only requires a single dummy gate shared between the two cells. Another scaling booster is contact-over-active-gate (COAG), see the image to the top left. The metal stack has two layers of Cobalt and 10 layers of copper.

 Above are the widths and spacings of each layer. The scaling numbers are with respect to the prior 14nm node.

The manufacturing uses SAQP (self-aligned quad patterning) for the fin, metal0 and metal1, getting down to a pitch of 34nm for the fins. Above that, they use SADP (self-aligned quad patterning) for metals 2-5 at pitches down to 44nm. For the first time, they are using Co for the local interconnect layers and the contact layer.

The scaling is very aggressive, with close to 0.5X on m1, m4, m5, m6 (versus a conventional 0.7X representing a normal density doubling). There are 3 different SRAMs cells with sizes of 0.0312um2, 0.0367um2, and 0.0441um2.

Like everyone else, since there are scaling boosters (such as COAG), Intel has a more sophisticated measure of density than simply taking the tightest metal and the contacted poly pitch multiplied together (see The ASML Standard Node). The Intel measure weighs 6 parts of NAND density to 4 parts of scan flipflop density, which allows scaling boosters to show through. With a dig at Intel's foundry competition "it's better than the node name." Intel's 10nm process is arguably the most accurately named, a roughly similar node, for example, to GLOBALFOUNDRIES' 7nm node that was announced later in the morning (see tomorrow's Breakfast Bytes for details on that).

Using this metric, Intel is now at over 100M transistors per square millimeter (which is pretty amazing if you have been in the industry for any length of time at all—when I started, 10,000 gates was a big chip). The result of all this is that SRAM density is doubling every two years, and logic is actually increasing faster, with 2.5X from 22nm to 14nm, and 2.7X from 14nm to 10nm.

FEOL

One big change (and a difference from other manufacturers) is Intel's use of cobalt for contact fill and at m0 and m1. They say that the use of a cobalt trench contact provides over 60% line resistance reduction and 1.5X contact resistance reduction. The contact line resistance is down 60% compared to tungsten.

As I already said, the fin pitch is 34nm. The fin width is 7nm at the middle of the fin height. It is manufactured with standard SAQP with spacer and sacrificial layers. Compared to SADP it has 4 additional steps (3 etch, 1 deposition) and no additional lithography. The result is fins that are tighter, straighter and taller.

The fin height can be varied a little, depending on the application. In the Q&A Intel said that they can do a range of about 10nm, 5nm up or down. 5.46nm is a bit less than the mid-range of that 10nm.

The shared dummy gate at the cell boundary saves one poly track per cell, roughly a 20% area saving for standard cell logic. COAG enables a reduction of the cell height, giving a 10% area saving. The COAG is self-aligned, needs an additional etch stop over gate and for contact. There are just 3 additional steps (one etch, deposition and polish) compared to a normal contact. 

The electricals are good, with excellent short-channel effects, good drive current, and good subthreshold slope of 75 mV/decade. Ring oscillator performance is 20% better than 14nm at the same leakage. Reliability is good with TDDB for 10nm better than 14nm.

BEOL

The above picture shows the metal stack. Metals 2-5 are SADP with pitches down to 44nm. Cobalt cap gives 1000X EM improvement versus pure copper (although nobody uses pure copper, so this is a bit of specmanship). Metal 0 and 1 are SAQP down to 36nm pitch. Cobalt interconnect gives a 2X reduction in via resistance and a 5X EM improvement. In the Q&A they were asked about line resistance but "I've not run copper at these line widths for a long time so I can't answer".

Summary

Industry leading 10nm process, building on lots of experience with multiple generations of the basic fetures (FinFET, HKMG etc).

The big differences are:

• cell boundary isolation
• COAG (contact over active gate)
• cobalt local interconnect

As usual in these IEDM presentations, the manufacture reveals what they want and keep quiet about details like the exact number of process steps, masks and materials. They get the bragging rights without  giving too much away to their competitors.

Another point is that Intel's primary market is high end server processor chips. This is a high margin business, making the tradeoff of cost versus performance different from other semiconductor companies. In addition, it has captive designers and can, if necessary, dictate to designers limitations in the process (such as the unidirectional layers that come with SAQP/cut).

22FFL

Since announcing one process wasn't enough for one day, Intel went on to announce their reworking of their 22nm FinFET process to produce a lower power version aimed at mobile and RF. I would say that this is starting go be a trend. As Moore's Law slows, lots of designs are being done off the most leading edge node. However, there has been a lot of semiconductor learning from volume manufacture of more advanced nodes, and also the opportunity to target these non-leading edge nodes at the markets that they now serve, rather than the markets that they served when the processes were new.

This post is long enough, so I won't try and give all the details. Here are the high points:

• single-patterned backend flow for the first time
• high performance transistors exhibig 57%/67% higher NMOS/PMOS drive current (compared to the original Intel 22nm process)
• ultra-low power logic devices reduce bit cell leakage by 28X, enabling a new 6T low-leakage SRAM with bit cell leakage under 1pA/cell
• new RF device with optimized layout shows NMOS and PMOS fT/fMAX of (230GHz/284GHz) and (238GHz/242GHz)
• device details etc in the table below

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