Intel's Process and Packaging Roadmaps

There are only three companies that are on the real leading edge. As you probably know, Intel has been struggling to keep anything close to its tick-tock cadence of process nodes, with problems at both 10nm and 7nm. On July 26, Pat Gelsinger, Intel's CEO since February, gave a very detailed process and packaging roadmap, which he calls Intel's "IDM 2.0 Strategy". Of course, it remains to be seen whether its technology development problems are behind them, and whether the roadmap Pat laid out arrives on the schedule he detailed, which is very aggressive new nodes coming faster than one per year.

Intel also finally did something that I have been suggesting for years. It switched its process naming to be roughly equivalent to the naming used by other foundries. What was going to be its latest 10nm process ("10nm Enhanced SuperFin") will be called "Intel 7", and what was going to be called 7nm will now be "Intel 4". Having simplified its process naming, Intel immediately introduced a new wrinkle, calling their 2nm process "Intel 20A" instead of "Intel 2", since 2nm is 20 Ångstrom units. Of course, there won't actually be anything 20Â on a chip. With planar transistors, the process names were tied closely to the gate length. But once we went to FinFET and folded the transistor up, it just became a number and there is nothing that is16nm on a 16nm FinFET process, although non-technical journalists often talk as if that is the size of the transistors, as was the case in planar days. The process after Intel 20A will be "Intel 18A". which sounds like it will be some soft of CFET process with the P and N transistors stacked vertically. But that is at least five years away.

10nm is in high volume manufacturing in Oregon, Arizona, and Israel. It seems to still be called 10nm, and not Intel 10. After that, Intel announced:

Intel 7: Delivering an approximately 10% to 15% performance-per-watt increase over Intel 10nm SuperFin through FinFET transistor optimizations, including increased strain, more low-resistance materials, novel high-density patterning techniques, streamlined structures and better routing with a higher metal stack. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.

Intel 4: Providing an approximately 20% performance-per-watt increase over Intel 7, Intel 4 is the first Intel FinFET node to fully embrace extreme ultraviolet lithography (EUV), which involves a highly complex optical system of lenses and mirrors that focuses a 13.5nm wavelength of light to print incredibly small features on silicon. This offers a vast improvement over prior technology that used light at a wavelength of 193nm. Intel 4 will be ready for production in the second half of 2022 for products shipping in 2023, including Meteor Lake for client and Granite Rapids for the data center.

Intel 3: Continuing to reap the benefits of FinFET, Intel 3 is expected to deliver around an 18% performance-per-watt increase over Intel 4. This is a higher level of transistor performance improvement than typically derived from a standard full node. Intel 3 implements a denser, higher performance library; increased intrinsic drive current; an optimized interconnect metal stack with reduced via resistance; and increased use of EUV compared with Intel 4. Intel 3 will be ready to begin manufacturing products in the second half of 2023.

Intel 20A: Ushering in the angstrom era with two breakthrough technologies, PowerVia and RibbonFET. PowerVia is Intel’s unique, industry-first implementation of backside power delivery—eliminating the need for power routing on the front side of the wafer and providing optimized signal routing while reducing droop and lowering noise. RibbonFET, Intel’s implementation of a gate-all-around transistor, is the company’s first new transistor architecture since it pioneered FinFETs in 2011, delivering faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint. Intel 20A is expected to ramp in 2024. [See pictures.]

2025 and Beyond: Beyond Intel 20A, Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build, and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry. Intel is partnering closely with ASML to assure the success of this industry breakthrough beyond the current generation of EUV.

With the increasing importance of chiplets, putting multiple die into a single package, the package roadmap is also important. Intel has had two different 3D packaging technologies, EMIB (embedded multi-die interconnect bridge) and Foveros, which comes in three flavors (or rather it will in 2023):

EMIB continues to lead the industry as the first 2.5D embedded bridge solution, with products shipping since 2017. Sapphire Rapids will be the first Intel Xeon data center product to ship in volume with EMIB. It will also be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design. Beyond Sapphire Rapids, the next generation of EMIB will move from a 55-micron bump pitch to 45 microns.

Foveros leverages wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution. Meteor Lake will be the second-generation implementation of Foveros in a client product and features a bump pitch of 36 microns, tiles spanning multiple technology nodes, and a thermal design power range from 5 to 125W.

Foveros Omni ushers in the next generation of Foveros technology by providing unbounded flexibility with performance 3D stacking technology for die-to-die interconnect and modular designs. Foveros Omni allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes and is expected to be ready for volume manufacturing in 2023.

Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct enables sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

Intel Foundry Services Customers

Intel have over 100 customers in the pipeline for Intel Foundry Services (IFS). Two announcements Pat made during the presentation were that the first customer for advanced packaging foundry would be Amazon/AWS, and the first announced customer for Intel 20A is Qualcomm.

Watch the Whole Presentation

See the video Intel Accelerates Process and Packaging Innovations (it is a half-hour presentation by Pat and other Intel technology leaders, followed by nearly a half hour of Q&A):

There is also an Accelerating Process Innovation factsheet.

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