Breakfast Bytes Blogs

There are many perceptions about analog design that might have been true once. For example, all analog design is done by grey-haired designers with decades of experience wrestling the signals to the ground using just a polygon-based layout editor and a circuit simulator. As a result, there is a perception that Cadence's Intelligent System Design strategy is just about digital. This is simply not true. For a start, Intelligent System Design is about designing whole systems, which means a lot more than a digital chip. It means analog, RF, photonics, advanced packaging, signal integrity, connectors, barely routable printed circuit boards. And yes, layout and circuit simulation. It's not like they have gone away completely.

Every design is different, so it is not possible to completely generalize everything, but a modern system:

• Copper is being used less and less, and signals are moving to photonics (data centers) and wireless. Both of these require analog/mixed-signal design (and RF design, obviously for wireless connectivity, whether it is WiFi or 5G cellular).
• Systems are increasingly being packaged in advanced (3D) packaging. This allows new and attractive forms of integration where the analog and RF parts of the design can be constructed in the "best" process generation for the design, rather than having to make do with whatever analog capabilities, often limited, are available in the advanced node being used for traditional SoC integration.
• Low power is a top-level imperative for every design. For battery-powered devices like mobile phones, this translates directly into an attribute that the consumer cares about, battery life. For chips in data centers, the power used by the electronics plus the power required to get all the heat out again, can equal the cost of the servers and routers. For example, NVIDIA just announced their Grace Hopper system (combining CPU and GPU chips), which dissipates 700W.
• Cars are loaded up with sensors that typically require analog interfaces.
• Companies are increasingly paying more than lip service to sustainability goals, and one of the best places to attack is reducing power across the board. From power electronics, to RF circuits, to optical, all have parts to play in doing this.
• Companies increasingly want to manufacture designs in multiple foundries due to supply constraints. Some companies could grow faster but they cannot get enough silicon in the process node that the parts were originally designed in. For example, here's a quote from MaxLinear's last earnings call:

We were upfront of the shortages, at least in the beginning of these shortages where we have deployed engineering resources heavily. Actually, we’re spending a lot of money in trying to find robust long-term sustainable supplier relationships through diversifying our production base.

You can probably think of other reasons too, but all the above are reasons that design teams need an advanced methodology to design complex systems that are low power, incorporate increasing fractions of analog/RF/photonics, that require flexibility to change process nodes and packaging. By advanced methodology, I don't just mean adding increasing automation over time, but also the basic blocking and tackling of having tools that share databases and avoid all the to-ing and fro-ing that is necessary when tools don't share databases. Not only does this tend to be slow and inefficient, each time the data format is transformed, there is a loss of accuracy.

When I was at Cadence twenty years ago, I gave quite a few keynotes when we went on big road trips doing a day of presentations every day in a different city. I always opened with the same theme, that there are three things that need to happen: drive up the level of abstraction to handle bigger designs more efficiently, drive down the level of detail to handle second-order physics effects becoming first order, and increase the level of integration so that the first two trends don't kill productivity. I even wrote a parody blog post in EDAgraffiti days, and I re-published it last week as my contribution to April 1st mirthiness in my post The All-Purpose EDA Keynote.

Here we are twenty years later the basic message remains true:

• Drive up the level of abstraction, so we are doing RF design in RF terms, not polygons; so we can do photonics designs in high-level terms and not worry about the precise shape of every unit; increase analog productivity with added automation so analog design is done at the specification level, and so on. I don't know whether to put this here or under integration, but one key is to improve the performance of circuit simulation since it is a fact of life in anything outside of pure digital design (and often even there too).
• Drive down the level of detail, since otherwise, we cannot handle noise; EM emissions and interference, thermal, signal integrity in chips, packages, boards, traces, connectors, cables, antennas.
• Increase the level of automation and, especially, integration so that have suites of tools built on common databases with common semantics, common engines, and avoid the to-fro inaccuracies that I already mentioned.

Virtuoso is the cockpit for a lot of this. In fact, the most integrated solution of all is Virtuoso Layout Suite EXL. Let me focus on that.

•  Boost custom/ analog Advanced-Node Design productivity with targeted place and route (P&R) automation techniques
  • Accelerate layout implementation of the most advanced nodes, using row-based methodology and multiple pattern technology (MPT)
• Analyze electromigration and IR drop with Electrically Aware Design
  • Monitor electrical issues as your layout is created to avoid multiple design iterations and “over design.” Knowing subnet current flow allows for correct wire sizing, without excess parasitics
• Drive layout implementation with simulation intelligence using Simulation-Driven Routing
  • Correctly size every net segment and via as you route with the industry’s first simulation-driven routing (SDR) engine
• Efficiently model passive components with an Integrated Electromagnetic Solver
  • Quickly and accurately simulate high-frequency and RF circuits with a world-class selection of simulators such as Cadence EMX Planar 3D Solver and Clarity 3D Solver
• Divide and conquer with Concurrent Layout Editing
  • Allow a layout team to work on large layouts together for faster layout implementation, chip finishing, and routing
• Accelerate floorplanning and optimize routability with Design Planning and Analysis
  • Create optimal floorplans that combine top-down and bottom-up methodologies with congestion-aware hierarchical pin placement

See a video on that last point Introducing Design Planning and Analysis (4 minutes):

DesignCon

DesignCon is coming up this week. In particular, on Thursday 7th, Cadence is presenting a series of educational seminars, many on these types of topics:

• 9.00-9.45 am Sherry Hess No Exit Ramps Needed—Cadence's System Design Workflow Delivers Seamless In-Design Analysis, Reducing Turnaround Time and Minimizing Risk
• 11.00-11.45 am Ken Willis Overview and Challenges of Running D2D Interposers
• 12.00-12.45 pm Michale Rowlands (Amphenol) and David Correia Addressing 112G Connector+PCB Modeling without Having to Simulate with Terabyte Servers
• 1.00-1.45 pm Xin Chang (Meta) and Ken Willis MIPI C-PHY System Design Exploration and Optimization for Signal Integrity Analysis by Using Advanced Cadence Compliance Kit
• 2.00-2.45 pm Tony Chen and Jared James Mainstream Signal Integrity Workflow for PCIe 6.0 PAM4 Signalling
• 3.00-3.45 pm Wendy Wu The Future of 224G Serial Links
• 4.00-4.45 pm Kyle Chen and Suomin Cui Optimizing Interconnect through Application of Bayesian Optimization Using 3D EM Solvers
• 5.00-5.45 pm Karthick Gopalakrishnan Electrothermal Co-Simulation for PCB and Package Designs Using Celsius Thermal Solver

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