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Paul McLellan
Paul McLellan

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How Technologies Get into EDA

4 Feb 2020 • 6 minute read

 breakfast bytes logo When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different grouping from what we call CPG today, I had physical verification (remember Dracula? Vampire? Assura? Diva?) but not PCB. Of course Virtuoso and Spectre were there. Mixed-signal design was becoming more important, but the Custom IC and Digital IC groups barely talked to each other, had separate databases, with different semantics, and different approaches to scripting. We had also signed a big contract with a customer to deliver a mixed-signal design system a year later. I used to joke that we had no idea what we were meant to deliver, but it had a name and a delivery date. Anyway, we decided that mixed-signal design was clearly important and the only way to solve the silos of digital and analog was to merge the engineering and marketing organizations. So that's how I ended up running marketing for all of IC design, both custom and digital.

In that era, there was still a reasonable amount of VC investment going into EDA startups, and most tools were point tools. Cadence's modus operandi for a new product space was often to wait until the winner was clear and then acquire them. The motivation for this approach was two-fold. First, it was impossible to tell in advance who the winner was going to be until the customers had awarded the prize by purchasing lots of the product. Secondly, we had learned that the salesforce of the day couldn't or wouldn't sell any product for which there was not already a strong market pull. So it was impossible to get an internally developed product off the ground.

Salesforces: Hunters and Farmers

I like to characterize salesforces (or individual salespeople) as hunters or farmers. Hunters are what you need in a startup. They have one product to sell, and they need to hunt down someone for whom it could be important enough, despite the product being immature. Farmers are what you need in a big EDA company. They are often in a team with a single account or a few accounts, and they need to expand their footprint in that account. They are not interested in spending any time finding new small accounts, nor in selling immature products that can interfere with the sales cycle. See my post Running a Salesforce for more details on this. Cadence's salesforce was and is primarily farmers, which is why they have historically been poor at evangelical sales of an immature tool.

As an example, I've written before about Heck. This was a formal verification product developed at Cadence Berkeley Labs and then transferred into our normal engineering organization. I have no idea if Heck was any good or not, I'm not a formal expert, but the salesforce was unsuccessful at selling it. It was an immature product, even if it had the potential to be great (unclear), and no salesperson wanted their AE resources tied up maturing it, nor risk delaying their big deal over a tiny incremental amount of revenue. Formal was still somewhat of an evangelical sell (even Jasper had only been founded in 1999) and we were not equipped for that. Our salesforce was focused on closing large deals with the largest few dozen semiconductor companies. Eventually, it got canceled and Cadence filled its formal verification appetite with Verplex in 2003 and then Jasper in 2014 and now has a strong position.

 Synthesis

An area where I know a lot more is synthesis. In the mid-1990s, Cadence started to develop their own synthesis product called Synergy. I was VP Engineering at Ambit, and so we competed against Synergy. Obviously, it wasn't our strongest competitor! It had one huge weakness, which was that the Cadence salesforce wouldn't even try and sell it. They were used to doing deals that were "try and get the entire customer's CAD budget except for synthesis" and, tell me if you've heard this before, they didn't want to risk their AEs getting tied up, nor delaying their big deal, over a couple of copies of synthesis. As a result, Synergy only had one serious customer, Philips Semiconductors (now NXP), Cadence's then-largest customer.

In the end, Synergy went the way of Heck and was canceled. Cadence acquired Ambit in 1998, which is how I ended up here on my first tour of duty. One big reason Cadence acquired us, I believe, is because we won Philips Semiconductors, still Cadence's biggest account. Ambit had a fair bit of sales momentum elsewhere, not just at Philips, having gone from less than $1M one year to over $10M the next. But in some ways, Cadence acquired us too early even so. The salesforce still wouldn't aggressively sell the product (BuildGates). We then acquired get2chip too, and over the years synthesis technology got more and more integrated into floorplanning and place and route (P&R). Since we had a strong position there, the salesforce finally started to sell synthesis as part of a package. Today, the current Cadence synthesis and P&R products, Genus and Innovus, are much more tightly integrated. There is placement and global routing technology in Genus, there is rebuffering and restructuring in Innovus. The result is that using Innovus with Genus gets results that are 10-15% better than starting from netlists from other synthesis tools.

Signal Integrity

 Another domain, which I will talk more about in detail in a future post, was signal integrity. When I was running custom IC, signal integrity was going from something second or third order in the early 1990s to something that designers needed to worry about. Some of this was due to Moore's Law and the relentless march of process nodes. Each new node moved the interconnect layers closer together, and to overcome resistance the metal got thicker (vertically). Both of these increase the coupling between adjacent interconnect lines. As chips got bigger, buses got bigger too. Consider running a signal over the top of a 128-bit bus. I love the terms in signal integrity, the switching signal is the "aggressor" (the bits of the bus) and the signal affected (the line running over the top) is the "victim". Although each bit has hardly any connection to the signal above, at some point all 128 bits are going to switch together, and then all those small couplings add up to something significant for the victim. The worst case is that a signal fails to latch and the design is non-functional. But smaller effects are important due to their effect on timing.

I don't remember Cadence having any internal signal integrity development—if we did it was not very big. The market leader in standalone signal integrity analysis was Cadmos, so we decided we should acquire them, which we did. The team reported to me, and...

But this blog post is long enough already. Next time I will look at how new effects get into the EDA tool flow and the challenges for managing the transition from just needing verification to having to take account of the effect during creation. And subsequently how issues that used to be just in the chip get out into the package, the board, connectors, cables, and more. This is part of what we now call Intelligent System Design.

Tomorrow's post is The Signal Integrity Story.

 

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