• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Breakfast Bytes
  3. Jasper User Group 2020 Preview
Paul McLellan
Paul McLellan

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
Jasper User Group
JUG
cadenceconnect
JasperGold

Jasper User Group 2020 Preview

5 Oct 2020 • 3 minute read

 The biggest gathering of formal verification engineers in the world takes place in a few weeks — the annual Jasper User Group is coming up on October 21st and 22nd. It has been branded under CadenceCONNECT, specialized meetings that take place alongside the bigger CadenceLIVE event. Of course, the event is online, so to call it a "gathering" is pushing things a bit.

Webinar October 19th

If you are new to formal verification, or new to JasperGold technologies, it can be challenging to follow all of the advanced features and methodologies presented in the Jasper CadenceCONNECT customer papers. Cadence is offering a webinar two days prior to Jasper CadenceCONNECT on October 19 to cover the basics of formal and the JasperGold platform.  The webinar will include discussion of common formal deployment methodologies and demonstrations of some of the most popular JaspeGold Apps. 

This webinar will be open only to individuals registered for Jasper CadenceCONNECT and is planned to last three hours, 8:30am PDT to 11:30am PDT, including a break.  During the presentations, there will be AE's available to answer your questions via the chat interface.  You can register for the webinar when you register for the conference itself.

Jasper User Group

 The day will start with Cadence's Ziyad Hanna presenting The State of the Union: Formal Verification in a Distributed World from 8.15am to 9am (all times are PDT). Ziyad is the corporate VP in charge of all formal development based in Haifa. He is also a visiting professor at the University of Oxford. Ziyad will also be back at the end (almost) of the second day to give a technology update.

That will be followed at 9am by a keynote by Professor Moshe Vardi of Rice University. His presentation is titled Program Verification: A 70-year History.

Moshe is University Professor, Karen Ostrum George Distinguished Service Professor in Computational Engineering at Rice University, where he is leading an Initiative on Technology, Culture, and Society. His interests focus on automated reasoning, a branch of Artificial Intelligence with broad applications to computer science, including machine learning, database theory, computational-complexity theory, knowledge in multi-agent systems, computer-aided verification, and teaching logic across the curriculum. He is also a Faculty Scholar at the Baker Institute for Public Policy at Rice University.

Here is a bit of color I was given on three of the presentations:

  • The first Intel presentation (Wednesday at 10am) on Scaling Up Formal Verification on AWS Cloud. Intel’s case is “massive parallelism” on “hybrid cloud” but, needs some custom work for each different situation.
  • The Arm presentation on Project Zero (Wednesday at 12.15pm) is about Spectre and Meltdown-like issues with processors.
  • The second Intel presentation on the CNN-based Image Processor (Thursday at 10am) hits a red-hot application area so seems especially interesting.

The full details for rest of Wednesday is:

10am to 10.45am Scaling up Formal Verification on AWS Cloud Intel
10.45am to 12.15pm Break and Demos
12.15pm to 1pm Project Zero: Security Verification Using SEC Arm
1pm to 1.45pm Efficient Bringup of Designs without a Testbench: Leveraging TCL for Automatic Checks Silicon Labs
1.45pm to 2.30pm` Register Map Verification using JasperGold CSR App with Coverage Analysis Texas Instruments

Thursday

Thursday has a slightly later start at 8.30am. The whole day will wrap up with awards by 3pm. In between:

8.30am to 9.15am Formal Verification: A Novel Approach for Verifying a CNN-based Image Processor Intel
9.15am to 10am Power up Your SoC Integration with Power-Aware Connectivity Qualcomm
10am to 10.45am Formal Verification Signoff for Digital IP: Can We Use It? ST Microelectronics
10.45am to 12.15pm Break and Demos
12.15pm to 1pm A Novel Clock Gating Design and Verification Methodology to Ensure SEC Convergence Intel
1pm to 1.45pm Safe Clocking: A Formal Approach to CDC/RDC Verification Arm
1.45pm to 2.30pm JasperGold Technology Update Ziyad and Team
2.30pm to 3pm Best Presentation Awards and Closing Remarks Pete

Learn More

Here is the CadenceCONNECT Jasper User Group page, including the up-to-date agenda.

This is the registration page, where you can also add registration for the webinar.

 

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.