Kaufman Award Dinner: The Tom Williams Story

Wednesday night it was the annual Kaufman Award Dinner to honor this year's recipient, Tom Williams. To learn more about the history of the award, read my post Who Was Phil Kaufman? I also talked to Tom Wiliams in Italy last month, when the award was announced. You can read that in my post Figure-Skating Champion Wins Kaufman Award. It turns out that after that interview, Tom went on the Canal du Midi in southwest France—straight into torrential storms and flooding which destroyed many boats, luckily not including his (that's the inhabitants of his boat on the right, although later they ended up having to abandon their boat, too).

Kaufman Award Dinner

If you read my previous post about Tom Williams when the Kaufman Award was announced then you know that Tom likes to go and photograph polar bears up around Hudson's Bay at this time of year. This year, he wasn't able to go. Instead, he had to be at the Glasshouse in downtown San Jose to formally receive the Kaufman Award.

Sean O'Kane, who usually makes the Sunday Brunch videos with me each week, was the master of ceremonies for the evening, but Aart de Geus (he's the co-CEO of Synopsys, but I assume you knew that already) took over to introduce people who had worked with Tom. During the second half of his career, before he retired, Tom was a fellow at Synopsys so Aart was his boss.

Aart started off pointing out that Tom had many interests other than semiconductor test. In his youth, he'd been a figure skater, indeed the Eastern US champion. He'd had a lifetime interest in photography, perhaps because he grew up in Rochester NY, which was a sort of Kodak company town (although not the only company in town, IBM had a big operation there, and there is a well-regarded university). At the end of the evening, many of Tom's wonderful photographs were shown, but you can see them for yourself since he has a photography website.

Aart pointed out that the people who win the Kaufman Award need to have "excellence and impact." Tom certainly did that, being one of the big contributors to the transition in test from the old ad-hoc way of doing things, to the very structured and automated way that we do it today.

Aart introduced Leon Stok of IBM, where Tom had spent the earlier part of his career. IBM had a problem in that era, what we now call the "known good die" problem, or KGD. Their mainframes of that era had 100 chips together in a TCM (thermal conduction module). If one of those chips wasn't properly tested and the whole TCM didn't work it would be very expensive. Test in that era was done by using simulation vectors, and the simulation was used to both verify functionality and verify timing using gate-level timing simulation. Tom's big insight was to separate functionality and timing. This was the beginning of what we have today, where we verify functionality with simulation (or formal or emulation as well, these days), and timing with static analysis. It also meant that you had to have race-free designs, since you couldn't rely on timing simulation to check if those races were going to work out or not. But this also made it possible to do test in a more structured way, having a separate test and system clock.

In 1977 Ed Eichelberger and Tom wrote a paper called A Logic Design Structure for LSI Testability. This described level-sensitive-scan-design or LSSD. Despite the somewhat bland title, all chips today are tested using methods derived from that 40-year old paper.

Next Aart introduced Rohit Kapur. As I put it "I've worked decades with TWW as a manager, mentor, and friend." He worked for Tom both at IBM and at Synopsys. He pointed out that Tom didn't just work on scan test, he also did work on Iddq testing. In 1996, Iddq testing was hot, and saying anything negative about it was bad. But that didn't stop Tom, he built a team to help him say bad things about Iddq testing. In case you don't know, Iddq testing is an approach where you find one or more vectors where the chip should be doing absolutely nothing and drawing minimal current (q stands for quiescent). If the chip is drawing more than a threshold, there is probably a manufacturing flaw and it can be discarded without running the whole set of test vectors.

Next, Rohit and Tom worked on test compression. One lesson they learned was to have good titles for papers. They wrote a paper in 2003 but it was rejected with weird comments from the referees. They changed the title and resubmitted it in 2004, and this time it got rave reviews.

Next, Aart brought up Anton Domic, CTO of Synopsys. Antun took us back to the big problem that the semiconductor industry was facing, which was that the cost of manufacturing was down (have you heard of Moore's Law?) but the cost of test was not coming down. In fact, even with scan test, the tester time was going up with chip complexity, and there just weren't enough pins on the chip or the tester. You could run the graphs out and see that chips were going to become dirt-cheap to manufacture, but prohibitively expensive to test. Mentor came out with TestKompress and everyone realized that was the correct approach to getting more bang for the buck, or in this case, more vectors inside the chip per vector on the tester.

Tom Himself

Finally, Tom got to speak. He talked about Rochester and how both Kodak and IBM were big influences. Another big influence was Ed McClusky, who coincidentally was on my technical advisory board at Ambit. Tom called him up and said he was thinking of starting a workshop on test, and Ed encouraged him. Tom says "I became an honorary PhD student of his."

One challenge in test that Tom talked about, that I'd never heard of before (despite my having been VP of Engineering at a synthesis company), was that synthesis made yield worse. In a hand-crafted design, there are lots of timing paths and they are normally distributed, and with perhaps one critical path close to marginal. Synthesis doesn't like paths with lots of positive slack, it is wasting resources in some way. All timing paths end up being very close to zero slack, so it takes very little to go wrong for one of the paths to fail. A synthesis tool likes to make all the paths critical paths, just like a car manufacturing plant likes all the parts to arrive just-in-time.

Tom had learned from Oscar acceptance speeches and so thanked many collaborators over his career. But he finished by saying it was "an honor for test to join the pantheon." Semiconductor test is now regarded as a solved problem. However "software testing is still in its infancy."

With that, it was getting late, and time for a slide show of some of Tom's photos of Stonehenge (where he has been lucky enough to get to photograph it alone with just a security guard), polar bears, and more.

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