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Do you know what known good die are? Do you know what wafer sort is? Final test?
After a wafer has been manufactured in the fab, it usually (but not always) goes through wafer sort. This uses a special tester to move across the wafer and test each die. Remember, at this point the wafer has not been cut up and (obviously) the die are not yet packaged. So how does the tester actually even connect to each die? This is done by a special jig, usually created just for that one design, called a probe card. There are various ways to build these, but typically they have needles with points or springs that are carefully positioned so that when the probe card is lowered onto the wafer, it makes contact with all or some of the I/O pads on the die. Since they may have literally a couple of thousand probes, these can be very complex and expensive to create.
Once a die is contacted, the tester runs the wafer test program. This may, or may not, be the same as the full test program that will be used before the packaged chip is finally released to be sold. The reason it might be different is that the probe card has different characteristics from the package and so, for example, it might not be possible to run the test at the same speed.
Also, the tradeoff is different from final test. Indeed, if the yield is high enough, it might make sense to skip wafer sort completely. Any bad die will be packaged up, and will fail final test. So that wastes the cost of a package. But it doesn't waste the cost of the die since it was bad anyway. Thus it is a tradeoff as to whether discarding the occasional package is more expensive or cheaper than performing wafer sort.
In fact, that same tradeoff can be done at a more precise level. Does it make sense to run a full test during wafer sort, or an abbreviated one that will have the occasional escape? Testers are expensive and so every second of wafer sort has a cost. It might make sense to run a one-second test program instead of a ten-second test program if that gets most of the bad die. The occasional one that gets through will be discarded during final test for the cost of the package (and the cost of putting the die in the package).
Any die that fail wafer sort used to be automatically marked with a pen, although increasingly there is a move to inkless wafer sort, where the good and bad die are recorded in a database. Later, when the wafer is sawn up into individual die, any marked die (or die recorded as bad in the database) get discarded.
An additional complication is that many modern packaging approaches work at the wafer level for efficiency. Typically, this is handled by sawing up the wafer (attached to some sort of backing). The bad die are then removed, and replaced with good die from a different wafer. That way there is a complete wafer of good die.
Final test is what it sounds like. After the die has been packaged, then it is put on a tester and the full test program is run to make sure that the die was really good in the first place, and that the packaging was performed correctly (for example, if it is wire-bonded, that all the bonds were made correctly). Any die that fails final test is discarded. The rest are shipped to the customer.
Sometimes, for products like microprocessors, they are speed-graded at this point. Microprocessors are often priced so that the same design with a higher clock speed commands a higher price. If a particular packaged part can run at the higher speed then it is binned into the higher speed, higher priced class. Otherwise, it is the lower speed, cheaper part. Obviously, there can be more than two speed grades.
I'm going to use the term system-in-package for all the packages where there is more than one die in the package. That might involve an organic or silicon interposer, it might involve stacking die and using TSVs to connect them, it might involve some form of multi-die FOWLP (fan-out wafer level packaging), or several other technologies. For the purpose of this post, anyway, they are all the same. Here's the sort of design to imagine, although somewhat of a contrived example, with one of everything:
The economics of testing die that go into a system like this are totally different. If you do a half-hearted wafer sort that lets some bad die get through, then eventually the whole system-in-package will fail final test. But, unlike in the single die case I discussed above, not only will you discard a package and a bad die, you will also discard all the good die in the package, too, and perhaps an expensive interposer. Plus, the cost of packaging all the die, much higher than with a single die, will also be wasted.
This puts a premium on making sure that the die you put into the package are already tested as well as possible. They are known good die (KGD). This makes wafer sort not only compulsory, but it is compulsory to make sure that it is as good as possible. Every escape will be very costly, taking down several other die as collateral damage. A bad die is thus very expensive.
If you read anything about these advanced forms of packaging, you will often see KGD (or, less often, written out in full as "known good die"). This means die that have been tested as much as possible to ensure that we never (well, hardly ever) package up a die that will eventually, and expensively, fail final test.
Sometimes you will read about the "problem of known good die". This is the challenge of ensuring that bad die do not escape into the packaging and final test process, and doing it in the most economical way. One of the challenges of 3D packaging, apart from mastering the packaging technology so that it yields effectively, has been developing cost-effective ways of ensuring KGD.
Another problem in final test in some systems in package is that the tester only has access to the package pins. Since test today normally means scan test, that means that it is necessary to get to the scan chains on each die. Stacked memories have the same problem although they don't use scan test. For an interposer-based design, this is not too difficult. But when die are stacked on top of each other, there are probably no routes to the upper die without going through the lower ones. In the same way as you can't get to the third floor of a building without starting at the ground floor and going up through the second floor, test programs also go up elevators (yes, that's the word used) to get to the upper die. This requires adding special circuits to each die to either test that die itself, or pass the test vectors up to the next level.
KGD are essential as the input to any multi-die packaging technology, and the more die that are in the package, and the more expensive the packaging technology (silicon interposers being about the costliest), then the greater the premium on ensuring that all die are good.
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