Linley: Enabling Heterogeneous Integration of Chiplets Through Advanced Packaging with AMD/Xilinx

At the recent Linley Fall Processor Conference, the first day wrapped up with a presentation by Ivor Barber of AMD, where he is the Corporate VP of Packaging. He started with an introduction to chiplets which I will skip. In fact, I think he ran through it very fast anyway, since the day had opened with a keynote by Suds Sudhakar of Cisco on the same topic, which you can read about in my post Linley: Chiplets for Infrastructure Silicon.

Two of the pioneers of 3D-ICs of all types were AMD and Xilinx. They both started in 2015, with AMD adding HBM to a processor and with Xilinx building the world's highest capacity FPGA (at the time) by putting multiple FPGA die onto a silicon interposer. And, of course, on Valentine's Day this year, AMD acquired Xilinx, so both pioneers are now the same company. Unbeknownst to me, Cisco was actually ahead of this, starting to use chiplets even earlier but not telling anyone about it. Perhaps most amazingly, its first integration was to put logic and DRAM in the same package, which required them to design its own custom DRAM (see the link above to the keynote if you want more details).

The packaging roadmaps for high-performance computing (HPC) use 2D chiplets that AMD calls IFOP (for Infinity Fabric on Package). The design on the left is what Ivor called "truly heterogenous" since it has four 7nm processor chips built in Taiwan and a 12nm control chip built by GlobalFoundries in the US.

The next step on the graph, 2.5D, is called EFB (for Elevated Fanout Bridge). EFB allows die that are next to each other to be connected.

Finally, to full 3D die-stacking, such as AMD's V-cache where it puts the cache on top of the CPU die, which has all sorts of performance advantages since you can't really get your memory any closer to the processor than that.

3D uses very different technology to the interposer-based approaches, known as a hybrid bond. Both die have to be molecularly smooth. One die is on the bottom, and the top die is flipped over. So both die have dielectric and copper. The dielectric forms a hydrophilic bond, then a low-temperature annealing step takes place, and the copper all bonds too.

There are several advantages to this hybrid bonding approach compared to micro-bump solutions:

• >15X interconnect density
• >3X interconnect energy efficiency
• superior thermal conductance

The SoC of the Future

The two aspects of building high-performance systems in the future are basically Moore's Law, continued scaling for key performance IP, and optimizing the technology and IP choices to minimize cost and power. Then the More than Moore part, leveraging advanced packaging to build the future SoC, with advanced 3-dimensional chiplets to enable heterogeneous designs. This delivers modular design supported by advanced packaging.

The next technology of the future is optical interconnect (OI). The goal with OI is to increase bandwidth by 100X while staying within thermal limits. OI will be the key technology for chip-to-system interconnect performance.

The Future of 3D Stacking

Ivor wrapped up with a look at the future of 3D stacking as the pitch of thru-silicon vias (TSVs) comes down. Advanced packaging can enable integration schemes not possible with monolithic designs.

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