Breakfast Bytes Blogs

The second day of the Linley Spring Processor Conference opened with a keynote by Jason Abt, the Chief Technology Officer of TechInsights, titled Foundations for the Future. There's a good chance you don't know who TechInsights is. Well, firstly, the company acquired the Linley Group late last year. They are headquartered in Ottowa, Canada.

TechInsights describes itself as:

Leading the world in microelectronics reverse engineering and building the content platform for the semiconductor industry

Or in a bit more detail, from their website:

TechInsights analyzes thousands of devices each year, from the system level right through to the silicon

• 14,000+ technical reports available for purchase
• Covering 40 years of technologies (1977 to today)
• Thousands of new projects every year:
• Teardown and analyze 750+ products
• Catalogue 6,500+ components
• Analyze 2,000+ chips

When he says "reverse engineering," he means that TechInsights buys electronics products and strips them down. Its specialty is decapping (unpackaging) chips and then gradually thinning them down to find out all the details of the manufacturing. Sometimes that requires aggressive approaches using tools not normally associated with microelectronics, such as getting the chips out of what I think is a piece of an electric car.

Note that all the images in this post are from Jason's presentation.

I actually think of reverse engineering as going further than this. To me, the term means to basically analyze a chip so that you can build some sort of equivalent copy of it or decompiling software so you can write your own version. But we'll go with Jason's version in this post.

Of course, stripping a chip down layer by layer involves some nasty chemicals and some expensive equipment.

Here is the semiconductor industry's process roadmap, with the names of all the processes.

And here are the novel features that make up the roadmap.

But this is a processor conference, not a process conference. So here is some analysis of various "mainstream" CPUs from 45nm to 7nm (which processor counts as mainstream obviously varies through the years. the manufacturer, and process nodes). On the left is cache density, and on the right is the die size.

This the age of More than Moore, so advanced packaging is increasingly important. TechInsights analyzes that too. For example, here is its speculation as to how the AMD V-cache is implemented (the cache is on top of the processor).

One interesting discovery Jason was proud of was finding these empty spaces regularly across. This is the AMD Ryzen 9. These holes are not being used for anything right now but are clearly for potentially adding TSVs to the empty spaces. The pitch between the holes (keep-out zones, or KOZ) is17um and the KOZ itself (the hole) is 6.2x5.3um. The keep-out zones are on all metal layers up to M11, where there is a TSV landing pad. There are no KOZ on M12 to M14. There is preparation for almost 23,000 TSVs on the Ryzen9. 

One thing he is less proud of is that when TechInsights analyzed the Apple M1 Max, they completely missed the interconnect areas that allowed the M1 Max to be put together to make the M1 Ultra with over 130 billion transistors. See my post March 2022 Update: Intel Video, India, Apple for more about the M1 Max and M1 Ultra.

Jason had many more interesting things that they had discovered, including some patent information. But I can't cover everything. He had nearly 50 slides.

Learn More

The TechInsights website. And the TechInsights blog.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.

.