Cadence's DDR Portfolio...and LPDDR5X-8533

At the recent CadenceLIVE Europe, Marc Greenberg presented Cadence's portfolio of memory interfaces. I'm going to keep to a relatively high level in this post, although he took deeper dives into many of the interfaces. One particular interface that he discussed was LPDDR5-8533 and its new PHY, which we hadn't actually announced at the time. But we actually announced this product today..

Marc started off reviewing many of Cadence's "firsts" in the DDR space:

• World's first DDR5 silicon IP
• World's first DDR5/LPDDR5 combo
• World's first 7nm GDDR6 IP
• World's first 7nm LPDDR5 IP

Those were test chips, of course. He then listed some of the successes in the real world:

• LPDDR5 IP with 24+ design wins
• DDR5 IP with with 40+ design wins
• Taped out 45+ unique DDR IP test chips
  • Testchips include Cadence PHY and Controller
• Application-optimized PHY and Controller IP
  • Customized PHY and Controller feature selection
  • Floorplan and package optimized
  • Custom hardening of PHY
• Futureproof with DDR/LPDDR new PHY architecture
  • Designed for 12+Gbps data rates
  • Adaptable for new memory module applications

The portfolio of interfaces that JEDEC has created can be confusing. The table above shows which interfaces to consider for different applications. There are four main areas of difference between the interfaces: performance (transfers per second), power, capacity, and cost. For example, HBM is the highest performance (due to 1024 connections) and capacity, but it is also extremely expensive, making it unsuitable for consumer and mobile products.

Cadence (and before that, Denali, which Cadence acquired in 2010) has been doing this for a long time. The historical roadmap is shown above.

The lowest row of colored block on the above graph, and the HBM blocks near the top, show how you can access one "unit" of memory:

• A single 32bit width GDDR6-16G device, optional clamshell expansion
• 64bit width of LPDDR5, one multidie package or two 32-bit devices
• One DDR5 DIMM using 64bits of data, assumes additional bits on DIMM used for ECC
• One stack of HBM with 1024bit connection

The other rows on the graph show how you can build up capacity and performance by using multiple interfaces in parallel.

The picture above shows where the various components fit in a system. On the left is the controller IP, always delivered as soft IP with a methodology to harden. In the middle is the PHY IP, delivered as a hard macro ready to be instantiated. Cadence finalizes the floorplan and bump map with the customer and then hardens the PHY. On the right is memory VIP (verification IP) used to verify the system matches the requirements of the type of DRAM being used.

The PHY can be delivered in several different floorplan configurations, depending on the SoC's requirements, as in the above images.

Cadence also provides bringup software. One of the challenges with an interface like this is that there are various registers that need to be set up with appropriate values depending on the exact environment in which the interface is operating. The old way was that a customer firmware engineer would write U-boot code for the CPU to boot DRAM and then spend days or weeks in the lab since nothing else can work or be tested until the DRAM works. The Cadence way is to directly access the DRAM controller and PHY registers through JTGAG and so bring up the DRAM interface first, typically in one day. The software allows 2D eye schmoo on any pin without probing. It is then easy to port the DRAM parameters into the chip-level firmware and bring the DRAM up. Here's a quote from a Japanese SoC vendor:

We use Cadence LPDDR4 IP in our fast turnaround video solution for digital video consumer applications, such as cameras and TVs. We succeeded in bringing up our LPDDR4 memory subsystem with the help of Cadence DDR IP bring-up software within an hour of receiving the chip back.

LPDDR5X-8533

Yesterday, Cadence announced LPDDR5X-8533 and a new PHY, which I already mentioned earlier. The above image shows the LPDDR5 testchip in 5nm. The new PHY is designed to operate at up to 12GT/s and LPDDR5X-8533 is the first product to use it (and it is on a testchip which is currently in fab in 4nm). This IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B) and the interface between the controller and the PHY is based on the latest DFI 5.1 specification.

A little bit of history. LP ("low power) off-chip DRAM was originally intended for battery-operated applications such as phones and laptops. But its bandwidth, capacity, and form factor allowed it to proliferate into non-traditional markets such as artificial intelligence and machine learning (AI/ML), automotive, and even some servers. It was introduced with a datarate of 6400MT/s. The chart above shows how DDR and LPDDR interfaces are matched to end applications.

Above is a diagram of the architecture of the LPDDR5X-8533 controller and PHY. It has:

• Improved Clocking
• Greater supply immunity
• Partitioned to ease customer implementations
• No top-level distribution of high-speed clock
• Hardened custom high-speed delay and I/O blocks
• N4P Tapeout

See a video demo of the LPDDR5X-8533 interface:

Summary

• Highly Configurable IP
  • Support for up to 16 ports
  • AHB, AXI-3, AXI-4, and Denali
  • CHI-C, D (single port only)
  • CHI-E on the roadmap
• DRAM protocols
  • DDR5/4/3/3L, LPDDR5X/5/4/4X
  • Combinations of above
  • GDDR6
• Memory VIP
  • Industry's most used and trusted digital VIP
  • Supports SystemVerilog, e, Verilog, VHDL, C/C++ and UVM test benches
• Pre-Silicon Validation
  • Transaction-Level (TLM) AT and LT models
  • Palladium and Protium models
  • FPGA models
• Silicon Validation
  • Rapid Bring-Up and Remote Debug software

Learn More

See the DDR PHY and Controller product page.

Berlin DDR Museum

Who knew there was a museum of memory interfaces in Berlin?

For anyone not old enough to remember before there was a unified Germany, DDR stood for Deutsche Demokratische Republik, the German Democratic Republic, or colloquially, East Germany.

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