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Today at the Electronic Resurgence Initiative (ERI) Summit in San Francisco, DARPA announced that Cadence was selected to support the Intelligent Design of Electronic Assets (IDEA) program, one of six programs with ERI to use advanced machine learning approaches to develop a unified platform for a fully-integrated, intelligent design flow for SoCs, systems-in-package (SIPs) and PCBs. These ERI investments are the next steps in creating a more automated electronics design capability that will benefit the aerospace/defense ecosystem and the electronic industry’s commercial needs. Cadence is one of 15 companies involved.
DARPA hinted at everything in a SKY talk at the DAC pavilion a couple of weeks ago, at which Andreas Olofsson presented DARPA is Building a Silicon Compiler. He talked about both IDEA and another program, the Posh Open Source Hardware program. I guess you could pick any word you wanted as the first one, the Gosh Open Source Hardware program, for instance. it's one of those self-defining acronyms like the GNU—GNU's Not Unix)—system (technically the name of Linux is GNU/Linux). Rick Merritt of EETimes covered it in DARPA Unveils $100M EDA Project.
Cadence has put together a program called MAGESTIC to fulfill the program charter over its four-year life. This stands for Machine-learning-driven Automatic Generation of Electronic Systems Through Intelligent Collaboration. The Cadence-led team includes Carnegie Mellon University (CMU) and NVIDIA.
The aims of MAGESTIC are:
Although the focus of the program is on DARPA's aerospace and defense needs, there are obvious commercial applications, which are also important since the US regards it as a strategic imperative to maintain technology leadership. The military purchases insignificant numbers of parts for most programs, and so they have increasingly switched to using COTS (commercial off the shelf) products when they can. That lets them focus their limited resources on areas where nothing commercial is available.
But leading-edge designs are increasingly difficult and expensive to design. I'm not sure I quite believe the half-a-billion dollar numbers that are out there, but for sure it takes a lot of people and a lot of months. DARPA cannot afford to put together the size of program that a Qualcomm, Intel, or Huawei assembles, with hundreds of engineers and hundreds of thousands of servers. These chips ship in the hundreds of millions, so can amortize the investment. Aerospace and defense programs cannot. In the commercial arena, the same problem exists since, for most markets, the volumes are not there. Even in automotive, the entire world ships "only" 100M vehicles per year, and it is unlikely that any semiconductor company will win every socket for a particular function.
The graph above highlights three problems:
"With over $100M in funding, the IDEA and Posh programs are one of the biggest EDA research programs ever", Olofsson apparently said while I was at the Cadence lunch. The goal is to change the economics of the industry and make it economical to design low-volume chips without a prohibitively high design cost, and on a shorter schedule.
The goals are to create a flow that is:
The program doesn't just address SoCs, although that is where the biggest costs occur. It also covers creating PCBs (see above).
At some level, MAGESTIC will use massive parallelism in the cloud (essentially as much compute power as is useful), with big data and machine learning techniques to substitute for engineers manually tweaking things and iterating. There is a huge amount of data available that current tools ignore: previous runs of the same tool on the same design, results of similar designs, accumulated knowledge about all the IP blocks, and so on. Experienced engineers already take advantage of this sort of knowledge when they decide how to alter a design or the tool control knobs to launch a new iteration. MAGESTIC is about making the tools do that themselves.
I know software engineers consider FPGA design to be a black art that only skilled wizards can approach. But I will be impressed if we can make IC design as "easy" as FPGA design. If we can really make it turnkey, so you launch a job and it delivers a fully-correct solution in ten days of crunching thousands of cores, that would change the world of system design.
There is an IEEE Spectrum interview with DARPA's ERI director Bill Chappell. There is a DARPA page about ERI.
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