Cadence and MathWorks Announce Flow from MATLAB to RTL

Today in Yokohama at CadenceLIVE Japan, Cadence announced a new MATLAB/Stratus flow integration jointly developed and supported by MathWorks and Cadence. This automates the path from MATLAB to Stratus and RTL allows an automatic flow from MATLAB through Stratus to RTL, and then onward through the Cadence Digital Full Flow all the way to implementation. Historically, I have attended CadenceLIVE Japan, but DAC is also this week and, for Covid-related reasons, there is no simultaneous translation into English of the keynotes and the main track. So I wasn't there in person—hopefully, next year!

When RTL synthesis took over the world in the 1990s, there was a lot of speculation as to what would come next. The received wisdom at the time was that it would be "behavioral synthesis" of some sort, taking the input language up a level to where the clock was no longer explicit. It turned out that this was the wrong answer, and the right answer was "IP". Big chips, by then starting to be known as SoCs, were designed with microprocessors, memories, peripherals, and specialized I/O interfaces. Most of the complex algorithms were implemented in software on the microprocessor. But it was clear that this was far from optimal for algorithms like radar and video processing, which required the higher performance that came with implementation directly into datapaths and gates.

MathWorks and the Flow

In parallel, MathWorks (then called "The" MathWorks) had a product MATLAB that became the standard tool for developing those sorts of algorithms. The problem was that MATLAB was one island, and synthesis was another island. There were two ways to get across the strait between the islands. One was to use HDL Coder from MATLAB to write out RTL. This worked fine, in the sense that the RTL represented the behavior in MATLAB, but it had no forward visibility of power, performance, and area (cost) of the resulting silicon.

The second approach is shown below. The results of MATLAB's analysis would be hand-coded into RTL, and the RTL could then be evaluated for the PPA that would result. The challenge was that if this was inadequate in some way (too slow, too big) then the RTL would have to be re-written by hand which is slow and time-consuming

Cadence developed and acquired technology that has culminated in the high-level synthesis product Stratus. This allows the gap between MATLAB and RTL synthesis to be automated, as in the diagram below. MATLAB produces synthesizable SystemC. Stratus can take that and optimize the micro-architecture and automatically create RTL that better meets PPA goals. This, in turn, can be synthesized to gates by Genus and eventually run through the physical design with Innovus to produce a block for the SoC. The big advantage of this approach, passing from MATLAB to Genus via Stratus, is that it is easy to tune Stratus to pick a different point in the PPA space and simply re-run it. For example, something like adding a pipeline stage, a massive change to do by hand at the RTL level, is accomplished easily.

MATLAB outputs the design via "HDL Coder" which creates not just the C++ for the design, but also the meta-data and the testbench. Stratus reads in the design along with libraries and timing constraints and optimizes the micro-architecture creating the RTL

The SystemC/RTL produced by this flow is competitive with hand-coded RTL, and is a lot quicker to produce. It is very easy to explore alternative architectures for the same algorithm, and so answer questions like:

What will be the power impact when running 5nm at 2 GHz using 16-bit fixed point math vs 13-bit.

What is the area tradeoff of using an II=1 pipeline vs. II=4 pipeline when running my design with 4 nm technology at 1 GHz? What is the throughput implication?

Example

As an example, consider an AES encryption module. This module was available in three forms: hand-coded RTL, Stratus-coded SystemC, and MATLAB code. This was implemented in GlobalFoundries 12nm at 500MHz. Synthesis and power analysis was done with Genus and Joules, with simulation data (for the power measurements) created with Xcelium. The table below shows the results:

Bottom line: Hand-coded SystemC is comparable to MATLAB-generated SystemC. Both SystemC inputs were smaller and more flexible than hand-coded RTL (obviously it is not possible to experiment with hand-coded RTL without completely rewriting the RTL).

Next Steps

The Cadence and MathWorks teams know each other and so can introduce you if you want to try this flow. The MathWorks team will guide you as to how to setup and access MATLAB and any other MathWorks' products. The Stratus team will work with you once the design has been exported and help you customize it, and ease any issues with flows through other tools.

 

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