CadenceLIVE Boston: The Current State of EDA Education

On the academic track at CadenceLIVE Boston, Matthew Morrison of the University of Notre Dame presented The Current State of EDA Education: Challenges and Opportunities. In fact, he won the award for best presentation on the academic track.

Matthew has appeared in Breakfast Bytes before. See:

• Andrew Kahng and Matthew Morrison on Industry and Academia
• Cadence Cloud Passport Partner Program

It doesn't really matter where you are in the semiconductor value chain, you are almost certainly workforce limited. You can't hire enough people. EDA and IP (such as Cadence) is certainly like that. A big part of the reason for this is that we as a nation are not doing a good job of educating students at the undergraduate level.

Some generic computer science education is, of course, a good grounding for EDA programming, too. But Matthew had depressing graphs that show just how much the trend towards computer science and away from electrical engineering has progressed. In the 1960s, computer science was non-existent, and it was all electrical engineering. Even when I was an undergraduate in 1975 at Cambridge, CS was a one-year course you could take in your third year. Now, 90% of EE/CS is CS and EE is less than 10%.

James Chew works in Cadence's Aerospace and Defense sector. In fact, as it happens, after CadenceLIVE Boston, I went with him to Wright Patterson Airforce Base to present a course. But he worked with Matthew on an appropriation request that it seems went nowhere. The issues are obvious to everyone inside, but not to anyone else.

One of the positives coming out of the Covid lockdown is that people who couldn't spell the word semiconductor, such as politicians and CEOs of automotive companies, suddenly could talk about nothing else. Finally, there was some serious attention to chips.

So now we have the CHIPS act. But shortages abound. You have probably heard that Intel is building two fabs in Ohio. But that requires 7,000 construction workers in an already booming construction environment and then will require boarding 3,000 skilled (or at least trainable) people to run the fabs when they are operational.

I was a "Mead & Conway baby", one of the first people to take a course on VLSI design at university (I was on the staff, but we ran it for everyone from undergraduates to masters students). It seems we are in the twilight of that era where VLSI classes are only offered as a niche topic. One problem is that deep learning and AI is the hot topic in town, and everyone wants to study that.

But Matthew has a plan to create the curriculum, and then deliver it through the cloud. In fact, he has run a course at the last couple of Design Automation Conferences to do that in a small way (for High-Level Synthesis (HLS)).

One area where I think I disagree with Matthew is fabbing at advanced nodes. There are two reasons. First, the NRE (fixed costs) for an advanced node is tens of millions of dollars just to make the masks. Of course, with multi-project wafers, that is amortized across a lot of design, but it is still high. And the other reason is that design at advanced nodes is incredibly challenging, requiring years of experience, which students simply will not have.

Obviously, EDA education (and VLSI education in general) is very highly leveraged into the entire semiconductor ecosystem. And as we discovered with supply chain shortages over the last couple of years, semiconductors are in everything from cars, to phones, to IoT devices, missiles, and...well, everything.

 

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