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At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16FF+ process (see the picture below). That is a lot of buzzwords, but the reason that this is important is, as Mellanox's Gilad Shainer said to me when I talked to him last week, "interoperability is the only way to prove standards compliance." This is especially true right now since the PCIe 4.0 standard has not been completed, but market pressures mean that end users cannot wait. The two companies obtained the 16Gbps results with four lanes running traffic concurrently, a typical configuration for next-generation servers, storage, and networking equipment. The Cadence PHY exceeds PCIe 4.0 architecture requirements in terms of insertion loss, while demonstrating a bit-error rate below 10-15.
Gilad is the VP marketing at Mellanox. They are the leading company developing interconnect solutions for the datacenter, providing server-server, server-storage, and storage-to-storage high-throughput datapaths. Their solutions support the two standard protocols, InfiniBand and Ethernet. They are the only company actually delivering end-to-end solutions with switches, adapters, software, and cables at 10Gbps, 25Gbps, 40Gbps, 50Gbps and 100Gbps.
The transition in datacenters from relying on 10Gbps as the mainstream to 25Gbps is predicted to be the fastest move ever seen. At the high end there is another fast transition from 40Gbps to 100Gbps. A lot of the need for bandwidth is driven by the need to handle the exponential growth in data and to enable real-time data insights. One rule of thumb Gilad had was that for every 100 smartphones there is a requirement for another server in a datacenter. With the number of smartphones predicted to soon exceed the 7B people in the world, that is a lot of servers needed to support them. In addition, there is a fast-growing business in data analytics ("big data") for things like fraud protection, drug discovery, and homeland security. This demand for bandwidth and better datacenter ROI drives Mellanox's business, since they connect about 20% of the servers being sold every year generating a revenue of about $650M.
One key technology in increasing bandwidth is PCIe. The new version, PCIe 4.0, allows data rates to increase from 50Gbps to 100Gbps and up to 200Gbps in the 2017 timeframe. But it is not enough for a single manufacturer to produce a solution, it needs to be interoperable with solutions from other companies. One way to build solutions that are interoperable is to use IP which has not just been verified in silicon but also shown to be interoperable in the real world. Only by real-world testing is it possible to create an established ecosystem where all the datacenter components can communicate.
In addition to IP, Cadence also offers silicon-proven agorithmic modeling Interface models for use with the company’s Sigrity technologies to create chip, package, and board designs that deliver robust signal integrity to handle impairments such as crosstalk and insertion loss deviation. It would be a wild exaggeration to say that the combination of the PCIe 4.0 PHY with the tools for signal analysis makes design easy, but silicon-proven IP and tools tested in the real world make it feasible to do such designs under tight time-to-market pressures. There are boards for PCIe 4 for interoperability testing. The IP is characterized to TSMC 9000. Obviously, compliance testing cannot be formally done until after the 1.0 spec is available some time next year. In the meantime, interoperability testing is the only option.
There is more information on Cadence's PCIe 4.0 PHY on the SerDes page. The press release about the interoperability demonstration is here.
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