Coming up on 20th October is this year's CadenceConnect Mission Critical event. It will be a digital event. Note that all times given in this blog post are Eastern, not Pacific like many Cadence events. If you are on the West coast, don't connect at 10am to find you are three hours late.
The event will introduce you to optimized design methodologies for mission-critical electronics system applications like aerospace and defense (A&D) safety, security, 5G, and others. The event brings together Cadence technology users, developers, and industry experts for networking, sharing best practices on critical design and verification, and discovering new techniques for designing advanced silicon, SoCs, and systems.
After the keynote at 10am (see below), the rest of the day (until 2pm) will be in two tracks:
The keynote will be given by an Englishman called Paul who has a PhD in Computer Sciene and went to Cambridge University. All those things apply to me, but that is where the similarities end. Paul Cunningham is the Senior VP in charge of Cadence's verification business (SVG in Cadence-speak). His keynote is titled Computational Software for Intelligent System Design and Maximum Verification Throughput. Depending on just how you count, verification accounts for about two-thirds of the effort in designing an electronic system, and if you add in all the software development too it can be much more. Jet fighters have about ten million lines of code, an autonomous car is estimated to have about a hundred million.
10:30 am – 11:00 am (Bombardier) Automated Meshing and Adaptive Re-Meshing at Bombardier
11:00 am – 11:30 am (Northrop Grumman) Emulation Digital Twin for SoC with eFPGA
11:30 am – 12:00 pm (Medtronic) Dynamic Duo Verifies a Patient-Provider Telemedical System
12:00 pm – 12:30 pm (L3 Harris) Robust FPGA Verification and Quantified Metrics for Safety-Critical Missions
12:30 pm – 1:00 pm (Northrop Grumman) Continuous Front-End Design and Verification Metrics Analysis to Speed System Deployment
1:00 pm – 1:30 pm (Analog Devices) Fault Campaign Framework for ISO 26262 Compliance
1:30pm – 2:00pm (Nano Dimensions) Additively Manufactured Electronics (AME) From Design to Fabrication
10:30 am - 11:00 am (Motorola) Delivering Mixed-Signal Design in 22FDX MSOA Flow with Innovus
11:00 am - 11:30 am (Rianta) Power Optimization via Joules
11:30 am - 12:00 pm (Texas Instruments) Using Design Intent and Simulation Driven Routing for Power Critical Circuit Designs
12:00 pm - 12:30 pm (Analog Devices) Electromagnetic Simulation of Large Chip/Package Designs Using Clarity
12:30 pm - 1:00 pm (BroadPak) Large-Scale Silicon Interposer Design Methodology in Allegro APD+
1:00 pm - 1:30 pm (Rohde-Schwarz) Enhancing the Accuracy of RF Front-End Simulations with Standard Compliant Signal Processing
1:30 pm - 2:00 pm (Butterfly) Real Number Modeling for Mixed-Signal Verification
Fill out your survey at the end of the event and we'll send you a $10 gift card for a couple of coffees on us.
See the Mission Critical 2021 page, which includes a link for registration. The event will also be available for replay at some point.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.