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Today Cadence announced the latest product in the "us" series of next-generation tools for leading-edge nodes, the Modus Test Solution. I always think that test gets treated as a second-class citizen, but in fact it is a major contributor to the cost of a semiconductor product. In some cases, the cost of testing the die is higher than the cost of manufacturing it. But somehow it is the Rodney Dangerfield of EDA and doesn't get any respect despite the large sums of money involved. Every year, the chip industry spends roughly $4B on automated test equipment (ATE) for manufacturing test, according to industry experts. This cost must be absorbed into the overall production cost of each working chip coming off production lines.
Modern approaches to test involve a number of different pieces. All (or most of) the sequential elements (registers) are linked into scan chains. The scan chains are not driven directly from the pins but from a compressor/decompressor (CoDec) that expands a small number of bits to cover all the scan chains, and then compresses the results back into a small number of bits. This allows tests to be done that would require too many pins to be dedicated to test or multiplex in complex ways, and also reduces the amount of memory required on the tester.
This compressed test approach has two challenges. The first is that we cannot detect any fault with more care bits than there are bits in the scan cube. So we want lots of bits in the scan cube. But that means shorter chains, there are a fixed number of sequential elements to go around. However, the shorter the chains, the fewer faults that can be packed into the scan cube, so the less the compression for a given coverage. Coverage drops off unacceptably as the compression ratio goes up to 100X and above, requiring additional patterns to get the coverage back up again. This fundamentally limits how much compression is possible: too much compression and the advantages of the compression are wiped out by the need for more vectors.
The second problem is that the CoDec is typically located in the center of the die and wires run from the XOR compressor to each scan channel. The more scan channels, the more wires that are required to get from the CoDec to each scan channel and back again. This causes a lot of congestion, especially in the center of the chip. The congestion doesn't just affect the test logic but the entire design and so can impact performance of the design in normal operation. The picture above shows the CoDec (essentially a set of wide XOR gates) in the center of the chip in blue, and the wiring required to get to and from the various scan chains in red. If the die gets larger, it costs more, and so the financial advantages of reducing time on the tester are wiped out by the increased die cost.
Modus Test uses an approach called 2D compression. This leverages the two-dimensional nature of designs. Instead of going point-to-point from the CoDec to each channel and back, the compressor and decompressor are spread around the edge of the design, and a two-dimensional mesh is used to route the test data. With the same die size, due to the reduced congestion, the 2D approach can get 400X compression with the same wire length as 100X compression using the traditional approach (or, alternatively, about half the wirelength at the same compression ratio). In the above pictures, on the left is the traditional technology at 100X compression and on the right is Modus at 400X, using the same amount of interconnect.
The other insight is elastic compression which adds sequential elements to the decompressor, which has the effect of adding bits to the scan cube when required, but without making the chains longer. Compression ratios over 400X are possible.
As a result of these two changes from the traditional approach, Modus Test is a test solution that more than halves test time with no reduction in test coverage, requires no additional test pins, and has no negative impact on physical implementation.
For testing memories, Modus Test supports using a single shared bus and one memory-built-in-self-test (MBIST) controller to service multiple memories, which eliminate the impact of MBIST on critical timing paths in high-performance CPU and networking chips.
Typical results are:
As the old Miller Lite commercials (almost) said, "Tests great, less filling."