My Second Visit to imec

Back in 2018, I first visited imec in Leuven, just outside Brussels in Belgium. I wrote about that in my post If It's Tuesday This Must Be Belgium. My First Visit to imec. Well, this time, it was Thursday last week for my second visit to imec. Of course, for most of the last two years, there was little international travel, and Jade Liu, who handles international press visits, has had little to do for that aspect of her job.

I met with three imec technologists, which I will cover tomorrow. The imec Technology Forum (ITF) for the USA is on the Monday afternoon of DAC, and so there will probably be more details on some of this, so you can perhaps regard these as trailers for the real movie.

Today I'll talk about Cadence PhDs and the fab window tour (lots of good photos).

Giuliano Sisto and Mohamed Naei

I had coffee with Giuliano Sisto and Mohamed Naeim. Giulano was a Cadence PhD resident at imec, and now is an employee of imec. As it happens, the day I was there was the day after his PhD defense, and so his first day as Dr Sisto. His role as the Cadence PhD resident at imec is being taken over by Mohamed Naeim.

They have been doing work in two areas, based around Innovus. One is thermal analysis of 3D designs using Voltus and Celsius. The second is getting Innovus to handle backside power delivery networks. This is what it sounds like, putting the power and ground networks on the back of the chip and then delivering it with connections through the thinned silicon. To get Innovus to handle this, they actually trick it by putting a spacer on top of the real interconnect, then putting the backside power network on top of that and letting Innovus connect it up. Later, that top layer is moved to the actual backside of the wafer/chip.

Mohamed is now working with Giuliano to continue the work, looking at putting more signals on the backside. The obvious first candidate is the clock, since CCopt can be used to handle that. But any signals that have to go a long distance can benefit from the improved parasitics of long runs on the back as opposed to threading its way through the normal frontside interconnect stack.

Fab Window Tour

Last time I was at imec, they were in the middle of enlarging the cleanroom and installing new tools (equipment). A "window tour" means that you don't go into the cleanroom proper but just the passageway outside where you can look into the cleanroom itself. You still have to put on shoe covers and walk across the sticky mats, but you don't have to wear a "bunny suit."

Here are a few pictures from this time:

Here I am in front of one of the bays. Much of the equipment is constantly being tweaked and without all their covers on, so these building site barriers are used to surround dangerous areas. Like on a building site, I suppose. Even so, they do look incongruous in a cleanroom. I bet the barriers are a lot cleaner than on any building site, though.

Last time, the ASML EUV scanner was nearer the window, but I was not allowed to photograph it since it had its sides off. That machine has been upgraded to this one, but it is harder to see. It is the big unit in the middle ground to the right, underneath the beams of the crane, that is required to bring it into the fab through a specially created window at the end of the building.

Here's another view into the cleanroom. I have a pretty good idea about much of the process by which a chip is manufactured, but I really don't know how to identify different pieces of equipment just from looking at them, especially as they pretty much all look much the same with their covers on.

Lunch

Let's see how good Belgians are at making Indian food. Or I think technically a British version of Indian food since chicken tikka masala isn't genuinely Indian. Verdict: "kip tikka" is pretty good.

 

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