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NVIDIA just released their next-generation GPU architecture called Pascal and a brand-new GPU device, the Tesla P100.
As part of their product promotion of P100 a couple of weeks ago, NVIDIA invited editors and gaming bloggers covering this latest development to visit their massive emulation lab. Blunty, an independent blogger, released a YouTube video made in the emulation lab, which you can see is full of Cadence Palladium XP and Palladium Z1 emulators.
Narendra Konda, the NVIDIA engineer explaining the emulation process (or, as Blunty puts it, the designs are "faked") discusses how, for a year, the GPU design is run on the emulator connected to a real PC running the operating system and the video games that they are using to exercise the emulated design. This method allows them to catch hardware and software bugs along with performance testing in a real-world context. The P100 contains 16-18 billion transistors.
The proof of the methodology comes when the chip is taped-out and sent to the foundry for fabrication. As Narenda says in the middle of the video:
When the chip comes back from the fab and we start bringing it up in our silicon bring-up lab, typically what we have seen is that in a few hours the chip is up and running and it is fully functional. And the reason that the chip comes up so fast, compared to any other company, is because all the up-front work we do here at NVIDIA. One of the most important things is what we do here in the emulation lab.
Although the latest design is for an x86 environment, Narendra also talks about bringing up the Playstation in the same lab using a real Playstation motherboard with the IBM Cell processor.
At CDNLive in early April, Melanie Bianchi of NVIDIA explained how they use Palladium to do system-level testing of their NVLINK high-speed interconnect. This allows them to do large emulations of multiple GPUs beyond verification of a single chip. In fact ,towards the end of the video Narendra talks briefly about how they "do put multiple GPUs into these emulators." The maximum capacity of the Palladium Z1 is 9.2 billion gates, which is about 35-40 billion transistors depending on the design.
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