TSMC OIP: FINFLEX, Analog Migration, mmWave, and Awards

Last week it was "OIP," TSMC's Open Innovation Platform Ecosystem Forum. My day consisted of attending the keynotes, where we were not allowed to take photos, followed by a press event (where TSMC gave us the slides!), followed by the TSMC award lunch. In the afternoon, I attended a couple of Cadence sessions which I will cover in the future.

I wrote about the announcements we made that day in my post TSMC OIP: N3E/N4P, 3DFabric, Analog Migration. I would say that one of the big themes of the day was advanced packaging, for which TSMC uses the name 3DFabric. I consider it to be the hottest area in semiconductors right now, packaging having been a comparatively sleepy backwater for decades.

Dave Keller

Dave Keller, CEO of TSMC North America, opened the event. As usual, he had some interesting statistics. This was the 12th OIP and three years since the last in-person event. This year it was hybrid, both in-person at the Santa Clara Convention Center, and online.

In 2021, there were 12,300 different chips. Typing this now, I realize I'm not sure if that was worldwide or just the US,  but so much of TSMC's business is in the US it probably doesn't matter that much. TSMC now has 10,000 people (roughly a Cadence worth) working on OIP. There are now over 50,000 titles in the OIP portfolio. There have been over 90 adoptions of TSMC's cloud.

And with that, he introduced L.C. Lu.

L.C. Lu

Dr. L.C. Lu is the VP of R&D for the Technology Platform.

LC started with the technology roadmaps (which were also included in the press presentation). As you can see, the backbone of the roadmap goes from N7 in 2017 to N5 to N3 (about to go into volume production) and then N2 in "the 2025 timeframe." N2 will be TSMC's first nanosheet process (also often known as gate-all around or GAA). Then there are derivative processes. N6 is a shrink of N7, and N6RF is a version targeted at RF designs. N5 goes to N5P, and then there is a shrink to two N4 processes, N4P for low power and N4X for HPC (I think). In the same way, there are three derivative 3nm processes, N3E, N3P, and N3X. Presumably, when we get there, there will be derivative processes from N2 too.

N3 is entering volume production with high yield and a fast product ramp

N3 also uses TSMC's FINFLEX approach, where the number of fins varies depending on whether the focus is power or performance, and the number of fins for P and N transistors can be different. As always, P transistors are weaker than N and harder to meet performance targets. As you can see above, at N16, TSMC used 3 fins. At N7 (and N6, which is just a shrink, so it has the same number of fins by definition) they used 2, and they used 2 again at N5/N4. At N3E they use the asymmetric fins with 2 fins for the P and one fin for the N transistors.

And as you can see from the above diagram, N3E also has a 2-2 fin version and a 3-2 fin version. I'll leave you to read the area, speed, and power differences if you want the details. Obviously, 2-1 fins is the lowest power and 3-2 fins is the highest performance (but you have to pay in both power and area, of course).

There is a lot of EDA optimization that goes with these variable numbers of fins since cells using them can be on the same wafer. The underlying semiconductor process is the same. For example, Cadence's digital full-flow puts higher-performance cells on the critical path to increase overall performance.

There were no details of N3P and N3X, just:

N3P and N3X provide further enhancements with production staeting next year.

Analog

TSMC has introduced very structured analog cells to improve cells. It offers analog cells for N5, N4, and N3. They will extend to N2 and N6 in the future. There are two major benefits to this approach. A boost in yield with pre-validated silicon and the fact that the very structured (like digital) layout leads to uniform oxide and poly density.  And then, there is an EDA-enabled design flow to automate moving cells from one process to another to gain 2-4X improvement in efficiency. That morning Cadence announced that we had worked with TSMC to implement the flow from N6 to N5/N4 to N3. N2 will be available next year.

TSMC analog cells to improve yield. TSMC offers analog cells for N5, N4, and N3, and will extend to N2 and N6. Two major benefits, boost yield with pre-validate silicon. Enabled EDA and design flow automation to gain 2-4X analog design productive. You can see the steps in the above diagram. Migrating the schematic, optimizing the design for the new process, and finally migrating the layout.

Automotive Design Enablement Platform

Not all processes are supported. The three automotive processes where the extra work has been done are 16nm, 7nm, and 5nm. N16 and N7 are all ready, with N5A coming by the end of the year. There was more information than I could write down, but one I did note was that N5A automotive grade standard cell and SRAM will be available. All N5A IPs pass ISO-26262 with ASIL-D or ASIL-B certification.

3DFabric

Dr. Lu then went on to talk about all the developments in 3DIC packaging and the new 3Dblox standard. But since that was the focus of the press briefing, I'll cover that in a separate post.

mmWave

I don't think it was specifically covered, but the other major development is the mmWave RF flow in N16FFC. At the start of the symposium, the press release about Cadence's involvement in this flow had not been finalized, but it came out by lunchtime (just in time for us to get an award for our work on it, see below).

Awards

At lunchtime, TSMC hands out the partner awards. Cadence won 6 awards, which is the most ever. This is not because we were especially wonderful this year, but that we worked jointly on so many projects and won an award for each:

• Support of the latest process nodes
• analog migration
• mmWave
• 3Dblox

If you have read Alice in Wonderland, you will have come across the race:

At last, the Dodo said, "Everybody has won, and all must have prizes."
"But who is to give the prizes?" quite a chorus of voices asked.

The answer was L.C. Lu, with Tom Quan as the emcee. Since TSMC has to be even-handed among all us EDA suppliers, we all got lots of prizes. Chin-Chi was there to receive some of them:

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