TSMC OIP Preview 2022

12 Oct 2022 • 2 minute read

tsmc logo I have pointed out before that you really only get two opportunities a year to get briefed on TSMC's roadmap. One of those is OIP, technically the Open Innovation Platform Ecosystem Forum. This year it is going to be in-person at the Santa Clara Convention Center on October 26th. It will then be an online VOD event on November 10th. If you are in Europe, it will take place on November 8th at Hilton Amsterdam Airport Schiphol, with the online VOD event on November 15th.

At both events, you will hear about:

Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies
Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications
Updated design solutions for specialty technologies enabling ultra-low voltage, analog migration, mmWave RF, and automotive designs targeting automotive and IoT designs
Ecosystem-specific TSMC reference flow implementations, P&R optimization, machine learning to improve design quality and productivity, and cloud-based design solutions
Successful, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers

The big-picture schedules for the US is as below. Europe has the same schedule, but everything is 30 minutes later:

8-9 am: Registration and the ecosystem pavilion
9-9:15 am: Welcome remarks
9:15-10:10 am: Enabling system innovation, and guest speaker
10:10-10:30 am: Coffee break and ecosystem pavilion
10:30-11 am: Three parallel tracks where TSMC will present:
- TSMC N3E FinFlex Technology: Motivation, Design Challenges, and Solutions
- TSMC 3Dblox: Unleashing The Ultimate 3DIC Design Productivity
- TSMC Analog Migration

At the end of the day, there will be a reception from 5:30-6:30 pm. Between the TSMC presentations in the morning and the reception, and with a break for lunch from 12-1 pm, there are three parallel tracks:

HPC & 3DIC
Mobile and automotive
IoT, RF, and other

tsmc oip banner

Cadence has several presentations in the US:

11-11:30 am: (Mobile track) Analog Design Optimization by Integrating MediaTek’s ML-based Engine within Virtuoso’s Analog Design Environment (jointly presented with Mediatek)
1-1:30 pm: (IoT track) Cadence mmWave Solutions Support TSMC N16 Design Reference Flow
2-2:30 pm: (HPC track) Simplifying Multi-Chiplet Design with a Unified 3D-IC Platform Solution for 3Dblox Technology
2:30-3 pm: (HPC track) Advanced Auto-Routing for TSMC InFO Technologies
4-4:30 pm: (Mobile track) Cadence Cerebrus AI-Driven Design Optimization Pushes PPA on TSMC 3nm Node
4:30-5 pm: (Mobile track) Kick off Your Design Success with Automated Migration of Virtuoso Schematics
5-5:30 pm: (Mobile track) Delivering Best TSMC 3nm Power and Performance with Cadence Digital Full Flow

Our presentations in Europe are:

12-12:30 pm: (Mobile track) Delivering Best TSMC 3nm Power and Performance with Cadence Digital Full Flow
1:30-2 pm: (IoT track) Addressing Reliability Challenges with Aging-Aware STA for Advanced Nodes
2:30-3 pm: (Mobile track) Achieving Best Power and Performance for Arm Cortex-X CPUs on TSMC Advanced Nodes with Cadence Digital Full Flow
3:30-4 pm: (IoT track) Cadence Cerebrus AI-Driven Design Optimization Pushes PPA on TSMC 3nm Node
4:30-5 pm: (Mobile track) Get off to a Good Start with Your Design with the Automated Migration of Virtuoso Schematics

Full Details on the TSMC Website

Here are details of all four events, each including a link for registration. I will be attending the US event in-person, so if you are going, I will see you there.

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