OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow, using only open-source software. The goal is to go from RTL to GDSII fully automatically. In a leading-edge process node. With zero DRC errors. In less than 24 hours.

I wrote about OpenROAD when it was presented at the Electronic Resurgence Initiative meeting in San Francisco in summer of 2017 in my post ERI: OpenROAD. The program is led by Andrew Kahng, a professor of EE and CS and UC San Diego. For more details on both Andrew and the goals of OpenROAD, see my earlier post at the link.

The motivation for DARPA is summarized in the slide above from DARPA program manager Andreas Olofsson's keynote at ISPD (and DAC) last year. The graph is a bit misleading, to be honest, since it shows Moore's Law (the blue line) on a logarithmic scale, and design cost (the red line) on a linear scale, and at first glance it looks significant that the red line is about to hit the blue line. But the message is just in the red line (and the bars): design costs are going through the roof. This is especially important for DARPA since their semiconductor volumes are so low that the cost of a program is the cost of designing the system, and the cost of manufacturing it is a rounding error. As another DARPA program manager, Linton Salmon, said in a different keynote: "In DoD, I've yet to see a total production that is more than the samples that we would send out in the commercial world."

The main participants of OpenROAD are a number of universities, along with Qualcomm (conveniently located just outside San Diego) and Arm (conveniently with a portfolio of foundation IP, along with processors of various complexities).

So how's it going?

Much better than I expected. Maybe better than even Andrew expected, since in a presentation at Cadence a couple of years ago, he called it a "moonshot".

VSDOpen2019

Khunal Ghosh organized a conference called VSDOpen2019 about open-source EDA tools and flows. I said conference, but it was entirely online. It took place from 9:00am to 1:00pm on Saturday morning in India. It was 8:30pm until after midnight on a Friday evening here in California, so I gave up my wild night of attending all the hot parties to attend EDA presentations. The opening keynote was by Andrew.

The initial focus of OpenROAD has been the RTL to GDSII flow for a digital SoC. The program will eventually encompass analog, system-in-package (SiP) and PCB, but you have to start somewhere. Whereas the traditional focus of an EDA flow has been the ultimate in PPA, even if the tools were hard to use and took a long time, the focus of OpenROAD is on ultimate ease-of-use and runtime.

The alpha milestone was starting with a moderate-sized design in a non-leading-edge process, namely 65nm, using Arm standard cells and other IP. In July this year, they went through the whole automated flow (synthesis, floorplanning, placement, CTS, global and detailed routing, chip finishing) and produced a DRC-clean GDSII. The design was based on the Vanilla Bean RISC-V core (4 SRAMs, 75K standard-cells). Andrew said that this milestone is important for two reasons: firstly that it is a proof of concept, and no academic program has ever achieved this before. Second, it is a breakthrough in detailed routing in academia, producing DRC-free output in a process that is not too far from the true leading edge. 

Andrew highlighted two of the tools used in the flow:

• Jim Cherry's OpenSTA. This is a commercial-grade STA timer that has been embedded in over a dozen EDA tools, including most FPGA flows. An incremental static timing tool is a key component of any modern digital flow, since one of the lessons of the last decade in EDA is that you have to have a single timing engine through the whole flow (as Cadence does, I'll mention in passing).
• RePlAce (yes, it really is capitalized like that) which is a Nesterov gradient descent placer, and underlies the automatic floorplanning, too. It was open-sourced in July 2018 specifically for the OpenROAD program.

Here are some shots of the July demonstration vehicle, after I/O and macro-placement and power-grid, after placement, after CTS, and after detailed routing.

Andrew didn't say how the PPA compared to a commercial flow such as Genus/Innovus. Typically, real designs get squeezed down until the number of DRC errors is low enough to fix by hand or with ECOs. Just glancing at the floorplan in the images above, there seems to be a lot of empty space so achieving a DRC-error-free design is less challenging. Nevertheless, I think doing it in a non-iterative flow with open-source tools is impressive.

The next milestone is V1.0, to do the same in a commercial FinFET process at 14/16nm. Then on to 7nm, packaging, PCB, machine-learning, and more. The era of autonomous design seems to be coming faster than autonomous driving.

Personnel

Andrew said that he thinks this program has one of the best chances of success of all the programs he has seen in his 30 years in EDA. Here is one reason. Well, two, actually. A big challenge academic programs suffer from, along with lack of real-world test cases, is lack of real-world experience. OpenRoad has done something I can only describe as a coup.

I mentioned Jim Cherry's OpenSTA above. Jim is a legend in the timing world, having created the Pearl timer at Cadence, and the Parallax STA, before creating OpenSTA. Jim has joined the OpenROAD program, which already uses his OpenSTA.

In July, Tom Spyrou joined as the Chief Architect and Technical Project Manager. Tom is probably best known for leading the team that created the timing engine that underlies PrimeTime. Then he worked for Cadence and led all our timing efforts. Most recently he was at Intel (he'd been innocently working at Altera and then suddenly he was at Intel). But he left Intel, moved to San Diego, and now has the office next to Andrew.

I've known Tom for decades and he worked for me at VLSI Technology where he created QTV (quick timing verifier). I assume there were earlier static timing projects in academia but QTV was the first one to get used in earnest. VLSI led the industry in signing-off all ASIC designs with static timing instead of gate-level simulation, starting in about 1990. Of course, all designs are signed off with static timing today, but back then it was considered "out there". Even by Tom, who was a little worried that all VLSI silicon was being signed off using the tool that he had created almost single-handed. I created VLSI's first circuit extractor and remember thinking something similar, that everyone's timing depended on the parasitics and transistor sizes my code calculated.

Github

More details on the OpenROAD project are on the OpenROAD website.

Everything is available under the OpenROAD project on Github. It all has a proper open-source license. It is not "academic use only" or "send me an email if you want to use it for a real design" as Andrew put it.

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