Breakfast Bytes Blogs

I've been working with Arm for longer than Cadence has. In fact, I was working with Arm before it was Arm, back when the Arm 1 was a processor developed by Acorn Computers (the A in Arm originally stood for Acorn). I described my early involvement in the creation of Arm in my posts Happy 25th Birthday, ARM and The Design that Made ARM. I think Arm was very lucky to be in the right place at the right time, just when chips got large enough that you could put other logic on them than just the processor and so the system-on-chip, or SoC, was born. This meant that every company that didn't already have its own microprocessor (as, say, Hitachi and Motorola did) needed either to design their own or license one. And there was only one processor available for license in that era. It was also when the mobile phone market started its explosive growth, and Nokia picked Arm, and as the #1 phone vendor it became standard (Ericsson, the #2 vendor who actually worked closely with VLSI Technology used the Z80, but then switched to Arm eventually when it decided an 8-bit processor was too underpowered).

The deal with Arm was basically that VLSI Technology (this was before the Compass spinout) would provide unlimited design tools for free in return for, I think, 5% of the company. All the early Arm processors were designed on VLSI Technology's tools. When Compass Design Automation was spun out of VLSI, VLSI kept the 5% of Arm. However, not unreasonably, Arm expected free tools from Compass and figured that VLSI should pay for them, but that never happened. I had the unwelcome task of negotiating an agreement with Arm whereby it would start paying for tools since we both knew it would be a big problem for both companies if Compass got nothing and provided everything for free.

Eventually, I became CEO of Compass, orchestrated a sale of the company to Avant! and it shut down the software since it was really only interested in the library (IP) business. Arm switched to using other tools. I went to be VP Engineering at Ambit Design Systems, Cadence acquired Ambit, and so I found myself in Cadence during the Ray Bingham as CEO era.

I talked to Paddy Mamtora to find out more about our relationship with Arm. He told me we had had several years of ‘support-oriented’ collaboration with Arm for Silicon realization tools. About 10+ years ago,  < 10% of the Arm cores were implemented using Cadence Digital Implementation tools.  Arm had acquired Artisan Components in 2004 and so was running a physical IP business, primarily standard cells and memories. When Virage Logic got acquired in 2010, that made us a preferred partner since we didn't compete with Arm in any area. In 2010, driven by a strong request from Texas Instruments to Cadence to collaborate with Arm,  Cadence CEO Lip-Bu Tan started Arm initiative at Cadence. Cadence’s GM for Silicon Realization Group appointed a small Tiger team led by Paddy to drive this uphill task to convince Arm to move to Cadence tools. To win this battle, it required significant improvements in the Implementation tools and our relationship with Arm and a massive OneTeam effort.

The High-Performance Core (HPC) Tiger team consisted of Product Engineer from RTL Compiler (Gopi Kudva) and Encounter products (Glenn Gullikson, Rob Lipsey – technical lead). During the initial days, the team had to deal with frequent crashes, inconsistent results, and a broken full flow. For any chip design, PPA (power, performance, area) is king, so we wanted to ensure that we had the best. The project was in Austin and the Tiger team went there every month, it started on a core codenamed Eagle that would become the Arm Cortex-A15. Today, our synthesis and physical design tools are tightly integrated, but in that era, our RTL Compiler and our Encounter people didn't even know each other. So not surprisingly, we were behind on PPA. However, after lots of efforts from R&D and monthly trips by the Product experts to Austin (wherein Project Eagle - A15 was being driven from), things began to change. GigaOpt engine was significantly enhanced, GigaPlace engine came, and in about a year and a half, Cadence was competitive on Performance (freq). To overcome and gain power advantage, Cadence acquired Azuro. With its concurrent clock and datapath optimization technology, Cadence PPA was now superior.

From that point onwards, it was all about the business proposition. A cross-functional team along with Paddy met with EMT to demonstrate that if we worked with Arm for the long term, then every customer on Arm might use Cadence and it was an opportunity of several hundred million dollars. Several resources were allocated to this task. The first engagement was with a mobile company that had better remain nameless in Austin. We did a competitive evaluation, showed better PPA, and won the business. This trend continued as Paddy partnered with Srinivas Iyengar from the Field Organization to drive further penetration of Cadence Digital full flow at the top Arm customers.

After achieving the best-in-class, a major inflection happened in terms of turnaround time (TAT) in 2015. The then GM of Digital Signoff Group (DSG) and now CEO, Anirudh Devgan launched Innovus and Arm was the first customer where Innovus was installed. Innovus showed 5X TAT on the toughest Arm cores at the time – A72 while improving PPA. This caused several top customers to shift to Cadence on their highest performance, lowest power Arm cores. About two years ago, we achieved an industry milestone in achieving 4GHz on the largest Arm core at the time on N5.

Our business with customers using Arm cores kept growing. Out of the box we continue to have leading PPA. A lot of people in Cadence, such as AEs and engineering, are very familiar with the Arm cores and have essentially become an “extended Tiger team”. We did a lot of training and knowledge transfer so that customers are well-educated and need less hand-holding.  Now, >90%  of customers are using Cadence tools for their Arm cores implementation, especially for their toughest, highest frequency, lowest power target designs.

Arm continues to use Cadence as the default flow although it supports the other obvious suspects. Joint collaboration between Arm and Cadence has resulted in Arm’s customers gaining a competitive advantage to produce best-in-class PPA in the shortest time to market. They have been able to reduce their risk and have the confidence to get the best PPA.

The next inflection working with Arm is Cadence Cerebrus, the AI-powered version of Innovus. Compared to PPA seen as the baseline (on a heavily tuned manual Arm flow),  when Cadence Cerebrus was run by Arm recently on their largest core at 3nm, they saw timing (TNS) improved by ~3.2X, Leakage improved by ~ 38% and utilization improved by 1.7%. Another design showed both 5% power reduction and 110+MHz improvement. This is just the beginning.

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