Package Assembly Design Kits

At the recent IMAPS conference, Cadence's John Park presented on Package Assembly Design Kits: What are they and how they can benefit the packaging community. John started by looking at some history and trends in the market, since heterogeneous integration means different things to different people. We have been doing multi-chip-modules (MCMs) and similar integration for decades, but in the last five or so years it has started to become more focused on doing SoC integration not by putting everything on one big die, but by creating smaller die, often called "chiplets" and integrating them in some sort of advanced package.

There are lots of advantages to this approach, depending on the details of the design, among them:

• Reduced NRE costs
• Shorter time to market
• Larger than reticle sized designs
• More flexible architectures (multiple processes)

PDKs

Prior to the creation of PDKs (Process Design Kits) in the early 1990s, the interface between the foundry and the design community was pretty much a design rule document and a SPICE deck for circuit simulation. As processes got more complex and design rule complexity exploded, this was no longer enough. The idea of the PDK was to encapsulate everything that IC designers needed to know about the manufacturing process to be able to design successfully. The PDK was designed to be read by modern EDA tool flows, so actual DRC decks replaced the printed DRC manual of old.

A PDK-Like Solution for Package Designers

Design has continued to get harder with more and more aspects that need to be considered. This has led to more and more aspects of the design that need to be considered by the package design team:

• Advanced multi-chip(let) silicon-based packages require specialized layout features and formal physical/logical verification capabilities
• Layout features specific to silicon substrate designs
  • Advanced filleting and trace widening
  • Progressive shape and pad degassing algorithms
  • High-capacity design support
• Mask-level accurate output data (GDSII) from substrate layout tool
  • Advanced arc vectorization
• Seamless integration with IC physical verification tool with feedback loop to layout
  • Mask-level DRC
  • Connectivity verification (LVS) of multi-chip(let) designs
  • Region-specific advanced metal fill (balancing)

It is time for package designers to stop guessing and so we need ADKs, in a manner analogous to PDKs. Another complication is that package designers are new to all these silicon issues, and IC designers are new to packaging. So what would go in an ADK?

You can see the components that John thinks should be in an ADK in the above table. Digging a little deeper:

Tech Files:

• These should be text files to keep things simple to read, write, compare, and share
• Substrate stack-up physical and electrical details
• Physical/spacing signal constraints
• Electrical signal constraints
• Constraint groupings
• Assembly/placement rules
• Test rules

Design Libraries and Models:

• Footprints
  • JEDEC standard BGA/LGA and SMD
  • Padstacks
  • STEP files (true 3D rendering)
• 3D Bond wire profiles
  • Model based on bonding equipment
  • Required for 3D DRC
• I/O models
  • Behavioral (IBIS)
  • Transistor-level
• Thermal/power models
  • Chip(let)-level thermal and power models
  • Static and transient power information

Design for Assembly:

• GUI-driven assistant to ease setup
• Unique to device DFA outline
• In-design direct feedback during component placement and move
• Table-driven with user-defined component categories
• Basic mode (table) and advanced mode (Constraint Manager)
• Rule definition setup can be done in a separate tool at the library level

Compliance Kits for Validation of Chiplet to Chiplet Interconnect:

• Based on similar compliance experience with PCBs
• Jitter tolerance
• Insertion loss
• Return loss
• Eye mask (for SerDes)

Rule Decks (Silicon Interposers):

• DRC
  • Including 3D stack pin alignment
• LVS
  • Chip(let)-to-chip(let)
  • System-level
• Metal fill
  • Smart metal balancing

Carpe Diem

Seize the day! John wrapped up with his plea that now is the time for ADKs:

• PDKs have been successfully leveraged by the IC design community for decades
• Packaging technology is exploding in complexity and designing in the dark is no longer an option
• New challenges face both IC designers and package designers and new approaches are required
• It is time for the package design community to embrace the ADK

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.