Pathfinding Beyond 5nm

One of the most interesting sessions that I attended at SEMICON West the week before last was titled Pathfinding Beyond 5nm. This was moderated by David Hemker, the CTO of Lam Research.

An Steegen, imec

The first speaker was An Steegen of imec. She basically gave a shorter version of the presentation from the Brussels ITF in May. See Secrets of Semiconductor Scaling. The brief summary is that the two key elements for the future of scaling are EUV coming into use for volume production and transitioning standard cell libraries for 9T (track) or 7.5T down to 6T or even 5T. The issues around EUV are well-known but probably the key ones now are line-width roughness and photoresist sensitivity. Reducing the standard cell heights requires some scaling boosters such as buried power rails, self-aligned gate contact, self-aligned vias, and so on.

Shu-Jen Han, IBM

The second speaker was Shu-Jen Han from IBM Watson, where he is responsible for "post-silicon research." His presentation was basically a state-of-the-world report on carbon nanotubes (CNT). He started by pointing out that power consumption is presently the fundamental limit making scaling so difficult. The only real way to reduce it is to reduce the supply voltage, but then we don't have enough drive capability with silicon. So what do we want in the next channel material? We want high mobility so that we can lower the supply voltage, but still have good drive, and we want lower sub-threshold swing so lower leakage power. CNTs fit the description.

IBM has successfully built CNT with 30nm gate pitch and 5-10nm contact pitch. The fundamental limitation is contact area, and one innovation is end-bonded contacts. They have demonstrated the first working FET with 10nm contacts. They have also demonstrated gate-all-round structures. They have managed to build high-yield inverters and they have 2-3 times higher performance and 2-3 times lower energy and a fixed power density of 100W/cm² (server microprocessor).

One of the problems with CNT is that when they are created, about 30% of the CNTs are metallic (conductors) instead of being semiconductors and these need to removed. One way is to grow on quartz and then transfer to the substrate, and post process to electrically break down the metallic ones. But with 6-10 tubes per device and a third of them randomly removed, there is huge device-to-device variation. Also, with even 10 tubes per device, billions of devices on a chip are going to turn out to be all metallic. They have developed a grow-purify-place approach where the metallic tubes are first sorted. They have demonstrated 99.98% purity using chromatography. They then use self-assembly to create trenches and place the tubes on the wafer. Since CNTs do not require high-temperature processing, they are compatible with the the BEOL, so there are opportunities to put them among the interconnect too, unlike silicon.

The final summary is that IBM has demonstrated sub-10nm channel CNT devices, and sub-10nm end-bonded contacts. Gate-all-round structure is possible. One key challenge is the separation of metallic tubes (need 6 9's purity). There remains a lot of work to be done, but CNTs are certainly promising as a future device.

Suman Datta, University of Notre Dame

The next device up for consideration was the tunnel FET (TFET). Suman Data of Notre Dame discussed. Until 2000 we had classical scaling, but since then we've not been able to scale the gate-oxide and also the voltage. So we have had innovations such as HKMG and strained silicon. But going forward, what do we do? TFETs are attractive because they get below 60mV/decade switching with competitive on-current. There are issues about what material to use. Silicon is easy but on-current is low, so we need mixed materials for source and channel. So they have created devices grown on indium phosphate (InP). The TFET is an asymmetric device in that the source and drain are not the same, as with traditional CMOS transistors, and there is gate-drain capacitance. TFET does best at low supply voltages, so ideally mix FinFET with TFET to create what Suman called "dim silicon." The biggest challenge is variation arising from manufacture of the tunnel barrier shape.

Dan Gittlin, Leti

The final candidate for consideration is CoolCube technology. Dan Gittlin is actually an independent consultant, but he has been working with Leti on this technology. The basic idea is to get a 2X increase in density not by moving to the next process node, but by stacking a double layer on the current process node. CoolCube technology leverages the mature steps from FD-SOI. The key step is creating a true monolithic inter-die via (MIV) with a pitch on the same scale as transistors, less than 100nm. CoolCube technology has a MIV density of 10⁸/mm².

There are two different approaches on how to build chips. One is to put NMOS and PMOS on both layers and benefit from a 50% area decrease and shorter wire length. The other is to put n-transistors on one layer and p-transistors on the other. This makes it possible to optimize the two layers separately. The biggest issue seems to be thermal.

CoolCube technololgy can reduce cost by about 50% and improves interconnect delay and capacitive load. Performance is improved and total power is reduced. In contrast to Moore's Law migrations, node n does not depend on node n+1 manufacturing tools and processes.

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