Breakfast Bytes Blogs

Well, that's a lot of tech gobbledegook in the title of this post. Here's what it means. This morning Cadence announced that its IP interfaces for low-power PCI Express (PCIe) 5.0 and for 112G long reach (112G-LR) are available on TSMC's N5 (5nm) process.

IP for PCIe 5.0

Let's start with a little context since you might already be hearing discussions about PCIe 6.0.

Indeed, I wrote recently, in my post The History of PCIe: Getting to Version 6, about the history of PCIe. Don't forget that 6.0 will be the next version and is not officially standardized yet, although nobody expects any significant changes during the standardization process, particularly to the signaling, which is going to switch from NRZ (one bit per clock cycle) to PAM4 (two bits per clock cycle).

So the current most advanced PCIe standard that is actually standardized is 5.0, and we announced:

• Immediate availability of IP supporting PCIe 5.0  specifications on TSMC N5 process technology
• And that the follow-on version on TSMC N3 process technology is expected to be taped out in early 2022

Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at designs for very high-bandwidth hyperscale computing, networking, and storage applications. With our PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient N5 SoCs with accelerated time to market. This is a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. Leveraging Cadence’s existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimized solution across the full range of operating conditions with a single clock lane.

Silicon Demo of Cadence IP for PCIe 5.0

Cadence demonstrates the IP industry’s first full 8-lane PCIe 5.0 subsystem solution on a single chip. The subsystem consists of our latest PCIe 5.0 PHY and controller technology interoperating at 32GT/s with leading OEM server platform and test equipment vendors. The subsystem solution is available in 7nm, 6nm, and 5nm process nodes with scalability to support up to 16-lane configurations.

IP for 112G-LR SerDes

Also today we unveiled our third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process. This has greatest applicability for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric SoCs. The innovative architecture of the 112G-LR PAM4 SerDes IP on TSMC’s N5 process offers 25% power savings, 40% area reduction, and better design margins over the second-generation architecture, satisfying the increasing needs for higher performance and power efficiency in today’s data centers. With the improved architecture, we now offer an enhanced DSP with multiple floating decision feedback equalization (DFE) taps to enable more robust performance. The 1-112G gapless data rate support provides excellent I/O flexibility for chip-to-chip connectivity for AI/ML accelerator SoCs. In addition, a 10X improvement in supply noise immunity greatly eases the SoC power delivery network (PDN) design.

The 112G-LR SerDes IP has multi-rate support, including 112/56Gbps PAM4 as well as 56/28/10Gbps NRZ for backward compatibility with legacy equipment operating at lower speeds

We have built a large customer base by enabling different variances of PAM4 SerDes supporting extra-short-reach (XSR), very-short-reach (VSR), medium reach (MR), and long reach (LR) interconnect standards. Through various 112G-LR SerDes design wins and deep collaborations with leading hyperscale and data center customers, we have incorporated specific enhancements in the third-generation product and currently have N5 test chips in-house that are undergoing characterization. We have been working closely with early adopter customers on deploying the new 112G-LR SerDes IP in their 5nm SoC development and we are now ready to engage broadly with customers to enable next-generation designs.

Silicon Demo of Cadence PAM4 SerDes IP

Learn More

For IP for PCIe 5.0, see the PCI Express (PCIe) 5.0 IP Solution product page.

For IP for 112G-LR SerDes, see the product page.

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