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Last Saturday there was a gala event at the Computer History Museum in Mountain View, where this year's fellows were inducted. Cadence had a table since one of the new fellows was Phil Moorby, the inventor of Verilog and Cadence's own first fellow. So I put on my tuxedo and went along.
In 1974, Phil's work on simulation started with his master's project at Manchester University, which straddled the hardware/software divide, testing hardware modules using the D-algorithm, a classic algorithm for automatic test pattern generation (ATPG). Lest that sounds easy, this was in PDP8 assembly language. Not only that, it was on a PDP8 that was so unreliable it would crash when the light switch was turned on or off in the room.
However, that turned out to be the perfect choice. When Phil went to Brunel University (very close to Heathrow Airport in Uxbridge) for an interview to do a PhD there, he told Professor Gerry Musgrave that he wrote the D-algorithm and got it working. "When do you want to start?" said Musgrave.
On a day to day basis, Phil was working with Peter Flake on a simulator called HILO-1. In that era, simulation was all about fault simulation. Systems were built out of small components such as the TI 74xx series. Nobody used simulation for verification since it was easier just to build a breadboard, but fault simulation was required to see whether a given test program actually detected all the faults of interest. For his PhD, Phil worked on dynamic timing analysis to go alongside the simulator. HILO-1 was what we would now call a unit-delay simulator. It had no timing, on each clock everything changed and it was assumed that the signals all propagated in time to meet setup and hold times ready for the next clock. Hence, the interest in adding dynamic timing analysis. HILO-1 had been written in assembly language for ICL computers (a British computer company that ended up in Fujitsu many years later). The work had been sponsored by the British Ministry of Defense (MOD) and they insisted HILO-2 be written in something portable. Peter Flake made the decision to use BCPL, which was a language originated at Cambridge and which I used for almost all of my undergraduate programming.
So Peter Flake and Phil worked on HILO-2, along with Simon Davidmann and a couple of others. By now it is 1980. Phil, like many other people, never wrote the dissertation describing the work he had done and never completed his PhD. Instead, he started working full time on HILO-2. The project moved from Brunel to Cirrus Computers and Genrad, a test company, started to sell HILO commercially.
Somewhere in that era, a group of us working on what we now called EDA but didn't back then visited Brunel from Edinburgh, but I don't remember who we met. But it is entirely possible that I first met Phil back in 1979 or 1980.
Meanwhile, on the US side of the Atlantic, Prabhu Goel is working at Wang and is tasked with bringing the best simulator into the company. After spending a couple of weeks at Brunel he picked HILO. Phil got to know Prabhu.
In 1983, Phil presented a paper at a conference in the US on fault simulatiion. Prabhu was at the conference. “Do you want to come over to the US and join a startup?” and a short time later Phil was working at Gateway Design Automation (still called Automated Integrated Design Systems), although he was back and forth between the US and UK until he got his visa.For the first six months he lived at Prabhu's house. Prabhu's vision for Gateway was not simulation but test and synthesis. Since logic simulators were so much slower than hardware there was still minimum interest in simulation for verification. IC simulation was all circuit simulation, and systems built out of discrete components were simply prototyped.
The first thing that Phil has to do is create a language for synthesis. Working with the rest of the team at Gateway, this was pretty much done in a month. However, based on all of his experience with HILO where the language would often make the simulator inherently slow, he thought about how to define the language to make the simulator go fast. It was not called Verilog at first but EST (expression of a system of tasks). When they started getting involved with Sun Microsystems they needed a name and Verilog came out of the brainstorming.
Having worked on the language for both synthesis and fast simulation, the next step was to build a fast simulator. There were three synthesis companies that had come into existence (Synopsys, Trimeter and Silc), and Synopsys adopted Verilog as their input language. Gateway decided they were too late for the synthesis market, that they should get a simulator out quickly. The focus was on compiling the language and getting adequate simulation speed, which Phil knew he could do having written several simulators by then. They surprised themselves by how quickly everything ran, especially the compilation phase.
The competition was starting to move away from other simulators to hardware accelerators, especially Zycad. Phil got the feeling that they could compete with hardware acceleration with new algorithms, the approach that became Verilog-XL, which ran blazingly fast at the gate level, almost hardware acceleration speed but without the seven-digit price tag.
In 1989, Cadence acquired Gateway Design Automation. Meanwhile, Chronologic Simulation had developed VCS which ran RTL simulation very fast by compiling it into C and then compiling the C (VCS stood for Verilog Compiled Simulation). It attacked a weakness of Verilog-XL in that it was very fast at gate-level simulation but when RTL got added in, it slowed down. VHDL was also another language that was competing for attention since it was in the public domain. Eventually, Cadence put the Verilog language into the public domain and it became an IEEE standard. That was the start of the situation that exists today where all the big three EDA companies (and some smaller ones) have state-of-the-art Verilog simulators.
Today, Verilog has been largely superseded by SystemVerilog. Simon Davidmann (who worked on HILO and was also one of the early employees at both Gateway and Chronologic) co-founded, with Peter Flake, a company called Co-Design Automation, and they hired Phil as chief scientist. Phil defined a superset language called Superlog. Co-Design Automation was eventually acquired by Synopsys and Superlog became the SystemVerilog that is almost universally used for IC design and verification today.
In his acceptance speech for the Computer History Museum fellowship, Phil thanked a number of people, most notably:
Watch the video made by the Computer History Museum that was shown at the induction ceremony:
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