Pieter Vorenkamp and IP at Cadence

Pieter Vorenkamp is the new(ish) senior VP and general manager of the semiconductor IP group here at Cadence. With both of us traveling a lot last month, it took about a dozen attempts to find a slot when we could talk, but the only slot was on my way from EDPS in Monterey to a weekend near Yosemite, which is how I found myself pulled off to the side of the road on the top of Pacheco pass, on the phone with Pieter. Given the cellphone reception up there, let me not recommend this location for a conference call.

Pieter was born and raised in the Netherlands. He has a degree from University of Twente and his first job was at Philips Research in Eindhoven where he worked for seven years. He then moved to France and worked for one and a half years at the Philips Semiconductors plant in Caen in Northern France (not to be confused with Cannes in Southern France). I actually visited it with a team from Cadence many years ago, I have no memory of why. (However, I do have a good memory of going to see the nearby Bayeux tapestry, which depicts the Norman invasion of England in 1066.)

In 1997, Pieter joined Broadcom and moved to Southern California. Since he has kids in high school, he will be staying at that end of the state, although he will be a regular visitor to San Jose, not to mention Bangalore and other places. I forsee a lot of plane flights in his future.

For his last six years at Broadcom, he was responsible for all engineering in operations. He ran the manufacturing interfaces, handling production issues, end-of-life programs, package engineering, production test, and the interface to technology development. Every Broadcom product first delivered samples to his organization for bring-up on production testers.

Prior to that he was in design management. In some ways, he has the perfect background for running an IP business, with both extensive experience of semiconductor design and also all the operational discipline. Among other positions he was chief architect for AMS and RF technology, and general manager for power management products.

He also had a lot of exposure to tier #1 customers at Broadcom and understands exactly what they mean by good quality. If there is an issue and a customer is on ship hold then it really doesn’t matter if it is the whole SoC or a small block of IP, it is a crisis that must be addressed. Pieter feels that other IP companies don’t think like that yet. They consider that “it’s only a small IP block”.

The IP business is of increasing importance to Cadence. Pieter’s mission is to build the business: expand the portfolio, increase quality, and increase engineering effectiveness. The IP portfolio consists of verification IP (VIP), the Tensilica technology, interfaces such as DDRx, USB, PCIe, and other digital and analog development.

All of Cadence’s business has the challenge of supporting new process technologies such as 10nm and 7nm in a timely manner. The challenge is even more acute in IP since many projects are complete redesigns, and everything from design, to manufacturing test chips and characterization end up on the critical path to Cadence’s customers’ success. Not to mention on the critical path to our foundry partners ramping to volume with real tapeouts.

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