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Today Cadence announced the new Protium X1 Enterprise Prototyping Platform. The previous version, the Protium S1 Desktop Prototyping Platform, was the size of a small refrigerator and intended to be beside an engineer's desk. The Protium X1 platform, like its emulator cousin, the Palladium Z1 platform, is intended to be housed in the data center and accessed over the network. As you can see from the picture, it fits in a standard rack. But it scales to as many as 32 racks, handling multi-billion gate designs.
This is the fourth generation of Cadence's FPGA prototyping systems, following RPP, Protium, and Protium S1. It can obviously be used standalone, but it has also been designed to be used alongside Palladium Z1 emulation, with a common compiler front-end, and the same SpeedBridge adapters to get to a range of peripheral devices. And if you don't have a Palladium Z1 platform of your own, then you can use one of ours (see Palladium Cloud for more details).
FPGA prototyping sounds like a way of prototyping a chip design to verify its behavior, and it certainly can be used that way. But its sweet spot is to allow software development to take place before silicon is available. It is higher performance than Palladium Z1 emulation but takes longer to prepare a design.
The diagram above shows the ancestry of the Protium X1 platform. FPGA prototyping rides the speed and capacity increases of the FPGA companies, initially Altera for RPP, but Xilinx for the Protium family. The Protium X1 platform is based on Xilinx Virtex Ultrascale VU440 arrays.
The Protium X1 platform has a blade architecture. Each blade is self-contained and can prototype 150M gates. At the next level, eight blades can be mounted into a single 19" rack for 1.2B gates/rack. The image to the right shows a full rack with one of the blades pulled out. Up to 32 racks (256 blades) can be ganged together for multi-billion gate designs/systems. The system can be shared at the granularity of single FPGAs, so a system can be used to prototype a single huge design or simultaneously prototype multiple smaller designs. Each blade can be shared by up to six concurrent users.
You won't be surprised to hear that the Protium X1 platform has a higher capacity than its predecessor—64X the capacity of the Protium S1 platform. A small design that fits in a single FPGA can run at 100MHz. A billion-gate design spread across multiple racks can run at 5MHz.
Protium FPGA prototyping and Palladium Z1 emulation are designed to be used together. When the RTL is not stable, emulation is great for debug. Once the focus switches to bringing up the software and the system, the Protium platform runs faster although with less visibility. They have the same compiler front-end, which makes it easy to transition from emulation to prototyping (once the RTL is starting to be stable), and back again (for full visibility when debugging tough problems). There is fully automatic partitioning across multiple FPGAs for the best possible performance for multi-array designs. Manual optimization allows for still higher performance with capabilities such as black-boxing and manual guidance for partitioning.
Debug can be done in separate windows for the software and for the RTL, as you can see in the above screenshots. One big advance in the Protium X1 platform over previous generations is that there is full visibility of signals. Previously, due to limitations of the FPGA arrays that formed the implementation fabric, you had to decide what signals to observe before compiling the design. That was clearly a drawback when you realized you left out a signal it turns out you needed, since you had to go back and recompile the design, which is a lengthy process.
NVIDIA has been using Protium X1 since "it is enabling us to develop our large GPU designs on FPGAs for the first time," Narendra Konda, head of hardware engineering, explained.
For more details, see the Protium X1 Enterprise Prototyping Platform product page.
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