Avoiding PCB Respins with Better Computational Software

14 Dec 2020

Avoiding PCB Respins with Better Computational Software

When I first came to the US, I started at VLSI Technology supporting a project called Bagpipe, mostly by getting the big Versatec plotter that VLSI had purchased to work at full speed and to spool jobs. Bagpipe was a chip for the future Mac, a sort of chipset to go with the Motorola 68000 processor, to do everything else such as sound and graphics. It turned out to have a power-ground short. Circuit extractors didn't yet exist. In fact, it would soon fall on my shoulders to write VTIextract, our circuit extractor. From that point on, things like power-ground shorts never happened. But without a circuit extractor, the only way to find the short was to print out the whole chip at about 20ftx20ft and color power red and ground green. That's why me getting the plotter working well was important.

So Bagpipe needed a re-spin once the short was found, since everything else seemed to be working. Unfortunately, Steve Jobs decided to cancel the project since he was worried that it would delay the launch of the Mac beyond the end of the year. Since this was 1982, and the Mac didn't actually launch until 1984, there was actually plenty of time for the respin. The software, not the hardware, was actually the critical path for the launch of the Mac.

Avoiding Respins

The message, though, is that re-spins are clearly something to be avoided. And the way you avoid them is by having better design tools. PCB re-spins are not as expensive as chip re-spins. But when they happen, the reason today is different from a few years ago. Re-spins don't happen because the router hooked up the wrong pin on the package. Allegro, and the infrastructure underneath it, simply don't allow that to happen. In fact, it is possible to trace signals from the board, through the package, and into the chip (using Virtuoso). That sort of error has been fixed by accurate connectivity checking, just like when I wrote VLSI's circuit extractor that made power-ground shorts a thing of the past.

Today, PCB re-spins happen because the extremely fast signals on the board have signal integrity issues, because once the entire design is put together, there are thermal issues, or because of some sort of EM problem. Some PCBs are big rectangles in a rack-mounted enclosure ("pizza box"). Those have their challenges. But think of the PCB inside your smartphone. Fast signals (RF even). No fan. Small physical size. Weird shape. Strict thermal requirements because it's in your pocket. Strict EM requirements because it is against your head sometimes.

In the past, it wasn't possible to analyze the entire PCB and its environment at the level of detail necessary to ensure everything was completely correct. Pieces of the circuit could be analyzed individually, but the entire design was too large for analysis on a single computer. The trouble with that approach is that the results have to be stitched together manually. This is less accurate than doing a complete analysis, and leaves open the possibility of doing something wrong without a tool to tell you that you made a mistake.

To give you a flavor of what a full analysis looks like, read my post Thermal Analysis of Protium X1. Protium is Cadence's FPGA prototyping system, but it could be any large modern system. The design was slightly over its thermal envelope. So could that be fixed with a baffle to direct more air over the offending chip? Or add another fan? Or a different heatsink? Or would the PCB need to be redesigned?

Tools for Analysis at Scale

In the last year, Cadence has released three tools that scale to do this sort of analysis on full systems:

The Clarity 3D Solver, analyzes signal integrity across an entire system, potentially including multiple PCBs, packages, connectors, cables or backplanes, and so on. In the IC business, we like to talk about "systems on chips" (SoCs), but in fact a system is never on a chip. It always needs a power supply or battery, often an antenna, I/O devices like buttons and displays, and so on. Even a birthday card that plays a tune when you open it needs a battery, a speaker, and some way to sense that the card has been opened. The Clarity 3D Solver scales to the largest systems, allowing you to verify signal integrity in the most demanding of conditions.

The Celsius Thermal Solver provides thermal analysis, including conduction, radiation, and airflow, and allows thermal analysis of large systems with complex conduction, airflow, and heat-generating chips.

The Clarity 3D Transient Solver provides EM analysis and electromagnetic compliance testing in software instead of an anechoic chamber. Final physical testing will probably still be required, but this tool allows early verification of both EM emissions and EM susceptibility, without the need to build costly hardware prototypes.

Computational Software

All three of these tools are massively parallel, multi-threaded, and distributed. The architecture allows the solver to be run on hundreds of CPUs optimized for both cloud and on-premises distributed computing. It has virtually unlimited capacity with near-linear scaling as compute resources are added. All of these tools are ideal for use with the Cadence CloudBurst Platform, which allows big jobs that require more servers than are easy to acquire in a data center to "burst to the cloud" and use as many cloud instances as necessary.

Under the hood there are three main engines:

A finite element analysis (FEA, sometimes called finite element method or FEM) used to mesh the design. This is fully automatic and requires no guidance from the user. The meshes can be very large—100+M elements is not unusual.
An electromagnetic (EM) analysis engine that takes the meshed design and does the analysis.
In the Celsius Thermal Solver, a computational fluid dynamics (CFD) engine for handling airflow (or any other fluid coolant), fans, heatsinks, and more.

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