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Recently the RISC-V Fifth Workshop took place at Google in Mountain View. As always, there were lots of presentations from academics. RISC-V has been a big hit there as the only instruction set architecture that is feasible for use in teaching and research, others being either too complicated or involving too many lawyers, or both.
But for me the most interesting aspect of the workshop are the companies producing silicon and providing routes to silicon. If RISC-V is going to be more than an academic curiosity, which I firmly believe, then it needs to have commercial chips and it needs to have systems built around them. I already talked about SiFive in RISC-V Available in Silicon. Another player is Codasip and their partners.
Codasip is a company based in Brno in the Czech Republic. They are a processor IP company. In fact, coming up to the workshop, their RISC-V IP was the most popular on the Design & Reuse website (and number 2 was Cadence's Automotive Ethernet IP, yay!). Codasip is trying to fill the gap between standard parts, which are easy but don't have differentiation (not to mention usually not being quite what you want), and ASICs, which are expensive to up-front and take a long time. They aim to provide "SoC design on an IoT budget."
Codasip have assembled a consortium of partners to deliver this, consisting of BaySand, UltraSoC, and CodePlay. The consortium consists of:
BaySand has a metal-only technology that they call MCSC, for Metal Configurable Standard Cell. They configure this with four layers of metal in their own fab. They have this technology available in 65nm and 40nm, giving up to 4M usable gates and metal-configurable RAM from 1-70Mb. This has the usual tradeoffs of this type of technology: much faster turnround, but potentially less flexibility due to what is and is not available in the base wafer.
Codasip's CPU technology is called Codix and the RISC-V version is called Codix Berkelium (RISC-V originates from UC Berkeley). The processor is highly configurable with:
The output of Codasip's tools give a complete software and hardware infrastructure so that the processor can be built via BaySand (or more traditional routes) and software can be compiled to run on it. While the technology has been in use for some time on Codasip's own processors, support for RISC-V is relatively new.
UltraSoc provides technology for debugging the hardware. Not so much for finding mistakes as analyzing why performance is not what was expected, or why sometimes DMA takes too long, or the processor sometimes hangs mysteriously. CodePlay provides support for a layered programming model from graph-based programming, normal C/C++, down to assembly language and VHDL. There is a focus on machine learning and vision, which will be important in many applications.
The testchip should be taping out soon and manufacturing should be 7-10 weeks, and will be made available to interested parties. There will probably be a development board, too. Just as RISC-V's "modest" goal is to be the instruction set architecture for everything, Codasip and their consortium of partners aims to de-risk RISC-V for any and every design. People at Codasip that I talked to during the workshop told me that their phone is ringing off the hook (well, ok, not that phones ring nor have anything to do with hooks anymore).
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