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Paul McLellan
Paul McLellan

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RISC-V Available in Silicon

5 Dec 2016 • 4 minute read

 breakfast bytes logoRISC-V FE310 chipsOne of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.

Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (32-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming "soon."

Well, it is now "soon." At the workshop last week, SiFive announced three things:

  • The FE310 SoC
  • The HiFive1 development board
  • That they are opensourcing everything

The FE310 SoC—Silicon Available

SiFive FE310 block diagram

The first announcement was the Freedom Everywhere 310 SoC. This is the first commercially available implementation of the RISC-V ISA. It is not the first silicon implementation; there have been a number of implementations within academia, especially, but not only, at Berkeley.

The SoC is implemented in 180nm. It runs at 320MHz. It has good power and performance numbers. SiFive claim:

  • 9X more power efficient than the Intel Quark
  • 2X more power efficient than the ARM® Cortex®-M0+
  • 10X higher clock frequency than Intel's Arduino 101 microcontroller
  • 11X more Dhrystones than ARM's Arduino zero

Their other chip is the Freedom Unleashed, which is a high-performance 64-bit implementation aimed at datacenter accelerators, networking applications, SSD controllers, and so on. This chip is on a longer schedule and silicon is not yet available. (The FPGA implementation was announced several months ago and can be downloaded freely into a Xilinx development board.)

The HiFive1 Development Board

HiFive 1 Development board

The FE310 is available on an Arduino-compatible development board called the HiFive1 for $59. You can buy it today and just play around with a RISC-V processor, or you can use it to start developing a real project that will eventually be implemented in some other way. You can buy it on CrowdSupply.

Open Sourcing

Everything is open sourced. The design is done in Chisel (see my post A Raven has Landed—RISC-V and Chisel for details if you don't know what Chisel is) and that has been open sourced (it generates the RTL but they don't want to support RTL on its own, that would be like supporting the assembly code for a software product instead of the C++ or whatever language was used). So the Chisel is open sourced along with the SDK for the HiFive1, the HiFive1 board. I don't think that I've ever seen an SoC where you can both buy the silicon implementation or download, for free, the RTL (well, Chisel, so a level up even) and do some derivative yourself.

I think that the main reason that SiFive can do this without it being commercially silly is thatt they expect to sell this chip (and derivatives) into the IoT market, which will be very fragmented. If the market is made up of a large number of designs that ship in relatively low volumes, it is unattractive for someone else to "rip off" the design and produce a high-volume version. SiFive's business model is a cross between a design service company and a fabless ASIC company. They expect people to approach them to do derivative versions of the FE310 with additional IP. SiFive will both do the design and manage the manufacturing process, delivering packaged, tested chips.

Freeing Silicon...Because Moore's Law Only Ends Once

I met with Jack Kang, VP product and business development. The motivation for creating SiFive was that traditional Moore's Law as a driver of the semiconductor business is over except in limited environments such as mobile. They feel that, with Moore's Law ended, innovation in silicon is going to happen at a lot of different nodes and different ways, not just transistor scaling. In IoT, most things will fail and it is necessary to try lots of things and see what sticks. If each throw costs $10M, you don't get many (or none). SiFive reckon that doing a derivative SoC design with all the up-front costs included should be less than $100K.

At a $100K price point, it is a lot easier for a small company with a few people and some ideas to bring it to market. I described it to Jack as like Amazon Web Services (AWS) for chips. Ten or fifteen years ago, starting a web company meant acquiring a lot of servers, somewhere to put them, people to manage them, and more. There were two big problems with this model: it had a high up-front cost, which was also a big waste if the company didn't succeed. But if the company succeeded wildly, it was also a problem, since it was hard to scale. Look at the problems that companies like Twitter had to scale when they hit it big. Software startups today do everything on AWS and can scale essentially infinitely. SiFive aims to make it low cost to get the first few chips, but also easy to scale to volume if the market loves the end product.

So their aim is to take the experience with open-source software and with agile software development, and extend that into the semiconductor industry with open-source agile hardware design, and making efficient silicon available to small companies, not just huge well-funded companies in large established markets.

Next: IEDM: The Big Decisions for 5nm

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