Home
  • Products
  • Solutions
  • Support
  • Company
  • Products
  • Solutions
  • Support
  • Company
Community Blogs Breakfast Bytes RISC-V Summit 2020 Preview

Author

Paul McLellan
Paul McLellan

Community Member

Blog Activity
Options
  • Subscriptions

    Never miss a story from Breakfast Bytes. Subscribe for in-depth analysis and articles.

    Subscribe by email
  • More
  • Cancel
risc-v

RISC-V Summit 2020 Preview

19 Nov 2020 • 4 minute read

  The third of three events taking place in the first three weeks of December is the RISC-V Summit. The RISC-V Summit takes place from December 8 to 10. You can read my preview posts about the other two December events from earlier in the week:

  • Cadence 5th Annual Photonics Event
  • IEDM 2020 Preview

Of course, the RISC-V Summit is virtual.

Let me give you a one-paragraph summary on what RISC-V is. It is an instruction set architecture that is open, in the sense that anyone can use it without cost (or royalties). It is not an open-source core (although those do exist), it is not a proprietary core (although those do exist). This is a slide from Krste Asanovic from the recent RISC-V Global Forum that shows what is available from whom (not a complete list):

There were also several presentations at the recent Linley Processor Conference about RISC-V, which gives at least one datapoint on how much traction the ISA is getting from the industry:

  • Graphics, Compute & AI Extensions Based on the RISC-V ISA by Think Silicon (Applied Materials)
  • Extending AI SoC Design Possibilities Through Linux-Capable Vector Processors by SiFive (Krste himself)
  • A RISC-V OOO Vector Processor by Andes Technology
  • Creating a RISC-V PC Ecosystem for Linux Application Development by SiFive (Yunsup)

Tuesday 8

Note that this is not the entire agenda, this is just some of the presentations that I consider especially noteworthy since I've seen presentations at prior RISC-V Workshops/Summits.

 Opening keynote by Calista Redmond, CEO of RISC-V International, 9:00am to 9:15am: RISC-V Unconstrained Growth and Opportunity. RISC-V International, now based in Switzerland, is the umbrella organization that "owns" the RISC-V name. Cadence is a member.

Keynote by Siva Sivaram of Western Digital, 9:15am to 9:30am: RISC-V for Next-Generation Storage and Compute. Western Digital is probably the company most committed to RISC-V. They have said that all the cores that they ship (billions in flash controllers) will be moved to RISC-V. They have designed their own core already, called SweRV and open-sourced it. You can read more in my post RISC-V Cores: SweRV and ET-Maxion.

Presentation by John Morris of Seagate, 9:30am to 9:45am: RISC-V Accelerating Innovation in Data Storage. I don't know how strategic RISC-V is to Seagate. Perhaps John will tell us in this presentation.

Keynote by unnamed presenters, probably Krste and/or Yunsup of SiFive from 9:45am to 10:00am: No title yet.

From 10:00am to 10:30am, there will be a live Q&A wit the keynote speakers.

Presentation by Tim Ansell of Google from 12:30pm to 12:50pm that is not (directly) to do with RISC-V but with open-source hardware in general: Fully Open Source Manufacturable PDK for a 130nm Process. You can read more about that in my post Open Source Hardware.

Presentation by Krste Asanovic of UC Berkeley and SiFive from 2:00pm to 2:30pm: RISC-V Vector Extensions for Scaling Intelligence to the Edge. Krste is the "father" of RISC-V and has been one of the main drivers of the vector extension.

Presentation by Art Swift CEO of Esperanto Technologies from 2:30pm to 2:50pm: Esperanto Accelerates Machine Learning With RISC-V. Esperanto has designed what I think is the most advanced RISC-V implementation, a super-scalar out-of-order core called ET-Maxion and a companion ET-Minion designed for ML. You can read more in my post RISC-V Cores: SweRV and ET-Maxion.

Wednesday 9

Keynote from 9:00am to 9:15am by Krste Asanovic with his "chairman of the board of RISC-V International".

There are a couple more keynotes not yet announced.

 10:00am to 10:30am: A fireside chat with Dave Patterson, the inventor of RISC (as in RISC-I), co-author of the standard book on computer architecture, and a contributor to RISC-V, too. I covered another fireside chat with him at SEMICON West in my post Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness.

10:30am to 11:00am: A live Q&A with the keynote speakers.

11:00am to 11:20am: A presentation of my old colleague from Ambit, Simon Davidman (who also ran CoDesign that developed Superlog that became SystemVerilog), RISC-V and SoC Architectural Exploration for AI and ML Accelerators.

2:30pm to 2:50pm: Another presentation on open hardware design not directly RISC-V related by Mohamed Kasem and Mohamed Shalem, A Complete No-Human-in-the-Loop Open-Source "Idea to Manufacturing" SoC Compiler. The flow goes from JSON to GDSII.

Thursday 10

12:00pm to 1:00pm (note that this presentation is an hour compared to most which are 15 or 20 minutes): A Guide to the RISC-V Cryptography Extension. The two presenters are Ben Marshall of University of Bristol and Barry Spinney of NVIDIA. NVIDIA was one of the first chip manufacturers to use RISC-V when they decided to replace the administrative processor on their GPU (which was previously a proprietary design) with a RISC-V core.

Note that there are lots of other presentations. I picked these ones out since I know who the presenters or the companies are from previous RISC-V Workshops/Summits.

Learn More

The agenda is spread over multiple pages but here is the first one. And there is an online registration page.

 

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.


© 2023 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information