RISC-V: Real Products in Volume

I titled my preview of the RISC-V Summit RISC-V Summit Preview: Pascal or Linux? since it is clear that RISC-V is really the only game in town inside academia, but it still hasn't conquered the commercial world. So it's already Pascal but not (yet?) Linux.

Some Highlights of the Summit

It is still too soon to say, but here are a few datapoints that I will either cover in more detail below or in future posts.

• Western Digital (plus Sandisk inside) announced last year that they would use RISC-V for all their processors. This year, they announced SweRV, which is a dual-issue in-order processor with impressively high performance. They also announced that they would completely open source it, along with some other pieces of RISC-V ecosystem.
• Qualcomm's presentation: “I end with an announcement: Qualcomm will be shipping RISC-V in a high volume product in 2019.”
• Google announced an UVM-based RISC-V verification platform that they will open-source.
• FADU announced the first shipping datacenter storage controller based on RISC-V with impressive performance/power numbers.
• SiFive sponsored the Linus Tech Tips Video #1 on RISC-V. It has 2.5M views on YouTube, Guancha, WeChat, Youku, CNX. They also (at Linley recently) announced a whole range of cores.
• During the summit, NXP gave away 700 Vega boards with Arm, RISC-V, and a lot of wireless cores on a single SoC. See picture of mine on the right.
• Esperanto gave details of their out-of-order RISC-V core, Maxion (that goes with their AI core Minion) including performance details. It will tapeout early next year. This is the highest performance RISC-V core that has been disclosed.
• Commercial core providers: Andes, Bluespec, Cloudbear, Codasip, Cortus, C-Sky, Nuclei, SiFive, Syntacore. Krste: "Never been a single ISA with this many commercial providers."
• Rick O'Connor, who runs the RISC-V Consortium, said that the question he gets asked all the time is whether anyone is actually shipping parts in volume. He said that in 2019, to give you an idea, there will be more than 10 million but less than 100 million chips containing RISC-V processors. There are 200 members in the foundation (see chart below). There were twice as many people (over 1000) at the RISC-V Summit as attended the equivalent workshop in 2017.

Krste's State of the Union

After Ric's opening welcome, Krste Asanovic gave the first presentation RISC-V State of the Union. He pointed out that RISC-V is enabling a new and important hange in business model. Before, you would pick your silicon or IP vendor, and go with the core they gave you. But with RISC-V:

You first pick the ISA (RISC-V!) and then pick the vendor. Plus you can add extensions without getting permission.

In particular, there are:

• Commercial IP Providers: Andes, Bluespec, Cloudbear, Codasip, Cortus, C-Sky, Nuclei, SiFive, Syntacore.
• In-house: NVIDIA, Western Digital, Qualcomm (actually announced the next day), and others not public.
• Open Source Cores: Rocket, BOOM, RISCy, Ariana, Piccolo, Hummingbird...

The memory model RVWMO has been ratified. That is actually odd since it means that the most complex thing has been ratified first, by the world's experts on memory models. The standard unprivileged mode public review eds on December 21st. The privileged architecture began public review that day and ends on January 25th next year.

Krste pointed out that standards take time. The existing base and standard extensions were 8.5 years in development and are only now being ratified. Large ISA modules take time and expert input. Debug took nearly three years. Vector extension is over three years so far. People need to get their expectations in line with what a real standardization process requires.

Facebook

One keynote that was a bit disappointing, given the venue, was Facebook's Rob Shearer, who talked about The 100X Problem: How to Redefine Silicon for Augmented Reality. This is the 100X performance/watt problem, although he says it is really 10,000X to get from a GPU to IoT. This means rethinking architecture and building systems entirely differently. I say it was disappointing only because it didn't have a RISC-V angle, and he didn't drop any hints what, or even if, Facebook is doing with RISC-V.

The 100X problem comes down to the things that we need to do in silicon:

• Optics and displays for AR/VR. Resolutions and fields of view are ridiculously challenging, so "optics is cool again."
• Audio. It doesn't get nearly enough attention, but it is an important part of the immersive experience.
• Interaction. "I don't want to click anymore, I want to touch things."
• Computer vision. "We are very visual creatures. It is our lowest power way to perceive the world that we are in."
• Artificial intelligence. "Everyone and their brother is working on a neural network now...but only about 1/3 of them are right."
• User experience. "Needs to be completely redefined."
• System design...and silicon everywhere.

We need dozens of customized cores in a whole system. We need to customize every single bit of compute. We need open and efficient profiling, a better way to work out what custom instructions we require.

Qualcomm

Greg Wright is the RISC-V Technical Lead at Qualcomm, with a background in computer architecture but also writing compilers. Qualcomm SoCs have a lot of cores, with code complexity going from hundreds of lines of code on little microprocessors, up to 80 million lines of code for base Android. There are also multiple roots of trust, so all the processors don't trust each other (for example, code on the application processor doesn't have free access to the cell network, and vice-versa).

He looked at how many ISAs they use in a single SoC and got up to six before he stopped counting. There is a big opportunity to harmonize many of the instruction sets. Probably not all of them, though. For example, a GPU is its own special thing. He didn't say it, but it is also the case that the main application processor shows through to the Apps running on Android, so that will continue to be Arm (at least for a long time). Potentially they can move code from one processor to another if they run the same instruction set. I'm not sure if he was thinking about doing it dynamically, while the phone is running, or just getting more flexibility during development.

The ISA is the contract between the hardware team and the software team. But the software team is much much bigger than the hardware team, so in practice, software never goes away, but hardware gets started over relatively frequently. This means that standardization is very important and fragmentation is the enemy. In particular, they need to avoid "an alphabet soup of options and configurations—that's not a feature when it has to live across generations."

He had an appeal to the community (mostly preaching to the converted at a RISC-V summit): Join the consortium. Join the working groups. Future lower end and high-end cores need to work nicely in a complex SoC environment. Security, virtualization, memory modes, interrupt delivery... and more. People who have worked at the high end before, in particular, should get involved.

He got to his summary slide. Then he had one last slide:

I end with an announcement: Qualcomm will be shipping RISC-V in a high-volume product in 2019. [Applause]

Future Events

RISC-V Workshop in Asia: March 12-14th in Taipei, Taiwan.

RISC-V Workshop in Europe: June 11-13th, Zurich, Switzerland.

Next year's RISC-V Summit (presumably in Santa Clara): December 3-6th (with the main stuff on 4th-5th if it continues to follow the normal format).

 

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