Breakfast Bytes Blogs

The second week of December was RISC-V week, the three-day RISC-V summit (or four if you are a member since Monday was "member day"). Tuesday opened with the keynotes being broadcast live. At least, that was the plan. The video platform pretty much melted down. I got a two-second snippet of video and audio, and mostly a spinning wheel. From watching the chat window, many other people were in the same position. Curiously, Silicon Valley seemed to have a lot of issues, while people were not having problems in Pakistan or Malaysia. I assume that the infrastructure that replicated the videos around the world was not overloaded in those places, unlike in Silicon Valley. Eventually, the conference organizers took everything offline and said they were "switching streaming platforms". That sounds a bit like changing a tire without stopping the car. There were some good witticisms in the chat stream to distract us while we waited. "None of the servers doing the streaming are running RISC-V" and "The x86 servers decided there was just too much RISC-V in the content". Everything was available later for replay, but initially, I had the same issues. But eventually, things seemed to start working somewhat normally.

Calista Redmond

The summit opened with Calista Redmond's keynote. She is the CEO of RISC-V International (now officially based in Switzerland to reduce geopolitical risk). Obviously, she welcomed everyone, but the interesting stuff was the statistics that she presented on the state of the ecosystem. Gartner is predicting strong growth in OEMs designing their own ASICs, up to 40% by 2025 (apparently it is 30% today). This was in a report titled Custom ICs Based on RISC-V Will Enable Cost-Effective IoT  Product Differentiation. The picture below comes from Gartner (from the same report, I assume):

Semico Research predicts the market will consume 62.4 billion RISC-V CPU cores by 2025, a 146% CAGR from 2018. The biggest share is predicted to be industrial, with 17B cores (blue in the graph below)

And Tractica predicts that the market for RISC-V IP and software is expected to grow to over $1B by 2025.

There are now more than 750 RISC-V members in 50 countries (including Cadence). In just 2020, membership grew by over 60% (and there's still a few weeks to go!).

RISC-V has already locked up academia almost completely. More interesting to me is adoption in industry. So here are some (more-or-less) commercial milestones from 2020:

• The European Processor Initiative finalized the first version of its RISC-V accelerator architecture, named EPAC, and will deliver the first test-chip next year.
• The RIOS Lab announced PicoRio, an affordable RISC-V open-source small-board computer available in 1H 2021 (think of a RISC-V Raspberry Pi).
• Imperas announced the first RISC-V verification reference model with UVM encapsulation.
• Microchip released the first SoC FPGA development kit based on the RISC-V ISA.
• Saifant Technology released the first RISC-V AI visual processing platform.
• SiFive unveiled the world's fastest development board for RISC-V personal computers.
• Micro Magic announced a fast 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V.
• The EU Horizon 2020 De-RISC platform for aerospace has achieved many milestones since starting just a year ago.
• The School of Computing at the Tokyo Institute of Technology developed a portable Linux RISC-V SoC design in just 5,000 lines of Verilog.
• Huami released a new RISC-V-based AI chip for biometric wearables.
• CHIPS Alliance announced enhancements to the RISC-V SweRV Core EH2, the worlds' fir dual-threaded, commercial, embedded RISC-V core and the SweRV Core EL2, an ultra-small, ultra-low-power RISC-V core.
• Alibaba unveiled its RISC-V RV64GCV core that will be used for its Xuantie 910 processor aimed and cloud and edge servers.

So what does RISC-V International actually do for its members?

• Technical deliverables to guard against fragmentation, via 47 different workgroups
• Compliance and verification suites
• Visibility of RISC-V through press and original content, and events (like this one!)
• Learning and talent, connecting universities, labs, and training partners
• Advocacy, including RISC-V ambassadors
• Marketplace Exchange, an online marketplace of providers, products, and services

She didn't mention it, but RISC-V International owns the name "RISC-V", and you have to be a member if you want to use it for your products. It is a registered trademark now.

One of the ways that the streaming problems were addressed was to put the first two keynotes up on the RISC-V YouTube channel. So you can watch Calista's whole keynote even if you didn't register for the conference:

Siva Sivaram

The second keynote was by Siva Sivaram of Western Digital. WD is the company most publically committed to RISC-V. They have committed that all cores in their storage controllers (over 2B per year) will transition to RISC-V. They have open-sourced the SweRV core and more IP to kickstart the ecosystem (and they are the headline sponsor" of the summit). Siva is President of Technology and Strategy. His presentation was titled The March of RISC-V: Next Generation Storage and Compute. By the way, Martin Fink, who was WD's CTO, and who gave the keynote last year, retired in September.

WD actually has three cores in the SweRV family, all of which are open-sourced. First is the original SweRV EH1 core, which has already been adopted by several other companies. The new core is the EH2, which is lower power and also dual-threaded, which is a big help in WD's main market involving a lot of I/O. The third core is smaller, the EL2, intended for sequencing. It has a 4-stage pipeline but is also higher performance than other microcontrollers WD might have picked.

Not directly RISC-V, but WD has also created a cache-coherent interconnect called OmniXtend, to allow devices other than the CPU to gain access to memory without having to go through the CPU.

WD has their first prototype product using a SweRV-based SoC.

You can watch Siva's whole presentation (even if you don't have registration for the RISC-V Summit):

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.