Samsung's 3nm GAA Process

At the recent Samsung Foundry Forum, HK Kang, the EVP of semiconductor R&D, took to the stage. He's in charge of advanced logic, DRAM, 3D NAND, mask. But that day he was just going to talk about Samsung's 3nm gate-all-around (GAA) technology, that they give the name MBCFET to (MBC stands for multi-bridge-channel).

The motivation for creating GAA technology is similar for the motivation for creating FinFET—better control of the channel. Planar transistor (on the left in the above diagram) was the basic transistor architecture since the invention of the MOSFET until about 20nm. At that point, the leakage became unacceptably high. When the transistor was in the off state, the gate only controlled the top part of the channel and current could sneak around the back, or, more professionally, suffered from short-channel effect.

There were two solutions to this problem, both of which Samsung Foundry provides. The first was FinFET. Make the channel a thin fin and wrap the gate around it. Since the fin is thin, no part of the channel is far enough away from the gate not to be controlled by it. The other was to keep with a planar transistor, but replace the deeper part of the channel with an insulator so that there was no way for current to sneak around the back, since there wasn't a back anymore. This is FD-SOI. If the insulator is thin enough, then it lets the substrate/body serve as a sort of second gate, not strong enough to turn the transistor off, but strong enough to either reduce leakage even further (reverse body bias), or to increase performance (forward body bias).

As we continued to march down the FinFET roadmap from 22nm/16nm/14nm depending on manufacturer, down to 5nm, the same issues started to arise. To keep control of the channel, the fins have to get thinner. To have high drive strength, the fins need to get taller. But as the fins get thinner, the contact resistance goes up (and other effects). Plus, they simply get too tall and thin to manufacture without them falling over. The solution is to go to GAA, so that the gate surrounds the channel completely. The earliest approaches used nanowires, circular wires, but it turns out that they are not really any better than FinFETs because the drive current is not high enough. Instead, a much wider wire works better, known as a nanosheet. Although they are sharply rectangular in the above diagram, they are typically more like ovals in photomicrographs. The photograph to the right is from a presentation IBM gave at the 2017 VLSI Symposium of their nanosheet development.

Although officially Samsung announced this process at SFF and there was a press release, they presented early details at IEDM in December. You can read that in my post IEDM Preview: 3nm and More.

HK said that Samsung looked at all four GAA technologies:

• Horizontal nanowire
• Horizontal nanosheet
• Vertical nanowire
• Vertical nanosheet

They benchmarked electrostatic performance, process integration, patterning, contact and routing, and designability. Their conclusions were that vertical nanowires are not good on any metric. Vertical GAA nanosheet has good numbers but is too difficult to integrate into the process so requires further breakthroughs. When I've seen imec present on roadmaps (that's one of their diagrams above), one of the big issues with the vertical transistors is getting a connection to the terminal (source or drain) underneath. Horizontal nanowires are better, but horizontal nanosheets are best of all since they have a larger effective transistor width Weff. Their conclusion:

MBCFET (horizontal nanosheet) is the most suitable post-FinFET architecture.

They actually started working on GAA technology a long time ago, with their first patents in 2002. Last year (at the IEDM paper I mentioned above), they demonstrated a fully working MBCFET SRAM.

There are several advantages of the MBCFET, and many areas where it is comparable with FinFET:

• Effective width Weff increase is secured vertically with no area penalty. The Weff for FinFETs can only be increased by adding more fins, causing area penalty.
• Design flexibility: most aspects of design capitalize on existing FinFET design. In particular, the digital flow is pretty much unchanged.
• Power and performance can be co-optimized since the width of the sheets can be tuned. This avoids the quantization that FinFETs have. It is possible to have both high speed (wide sheets) and low power (narrow sheets) on the same design.
• Analog design regains the ability to resize and match transistors, unlike FinFETs, which are quantized (you get an integer number of fins as the only way to vary transistor size).
• Samsung have "brilliantly" overcome the challenge of building narrow and wide nanosheets on the same wafer.
• They have demonstrated three different Vt threshold voltages for both nMOS and pMOS. MBCFET is a customized replacement metal gate technology.
• Self-heating is comparable to FinFET.
• Vt mismatch trend is comparable to that of FinFET, which is apparently a major issue in process variation.
• Reliability: TDDB (time-dependent dielectric breakdown) characteristics are comparable to FinFET.
• NBTI and PBTI (negative and positive bias temperature instability) characteristics are similar to FinFET.
• Samsung has built a fully functional high-density MBCFET SRAM. The noise margin is similar to that of FinFET. They are using it as a yield enabling vehicle.

When can you get one? Well, the version 0.1 PDK was announced at SFF, so you can start experimenting now. Risk production for 3GAE is late 2020, risk production for 3GAP is 2021, volume production 2022.

HK's final remark:

MBCFET the most promising semiconductor foundry platform beyond FinFET

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