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I attended the second Samsung Foundry Forum. As seems to be traditional for foundries, they had the usual rules that they wouldn't hand out the presentations, you couldn't record, you couldn't take photographs.
But you could take notes. So here are my notes. If you note the lack of images...well, now you know why.
The day opened with Kinam Kin, president of Samsung Electronics. He emphasized that Samsung is totally committed to Samsung Foundry. They started in the foundry business over 10 years ago. As of May 12, they reorganized and Samsung Foundry is now an independent business with its own budget. As was announced on May 12:
The current model has Samsung as a memory vendor and a foundry vendor and an OSAT (assembly). Driven by packaging, the future will be more turnkey, with the capability to put Samsung high bandwidth memory (HBM) and foundry all packaged together.
As regards to fabs, they are increasing foundry capacity in Korea (S1), and in Austin (S2). S3 ramp will be Q4 2017 in Hwaseong Korea for 10nm. They have 400K wafer per month of foundry, mostly on advanced nodes.
The keynote was given by Roawen Chen, SVP of Global Operattions for Qualcomm. He gave a little of the history of the fabless semiconductor industry. Twenty years ago in 1996, the top fabless company was Xilinx with $700M in revenue, and second was Altera (obviously still independent). Nobody, back then, really believed that fabless companies could reach the size of IDMs—only without fabs. By 2006, Qualcomm was #1, then Broadcom. Nobody believed that fabless companies could be billion dollar companies. But by 2016, Qualcomm was still #1 with revenue over $10B, without owning any fabs.
Foundries manage their capacity risk sharing with literally hundreds of fabless companies. The fabless companies have focused on design, while the foundries focused on generic manufacturing. That means that fabless benefits from manufacturing scale and loading flexibility, which offsets the margin stack (that both the fabless company and the foundry need to make a profit on each wafer).
Another thing that happens is that fabless capacity never retires, at least not for about 25 years. Vertical companies find this hard to compete with, since they often don't have any product to run in older fabs, whereas foundries can load new designs from completely different customers and markets. The scale has changed totally, too. In what Roawen called Fabless 2.0, there are only a few guys left in foundry. On the other hand, a single fabless company like Qualcomm can take 10M 8" wafers per year without a fab. That is many 12" lines just for one company.
The current model for a foundry factory is to start with computing and high-end smartphones. These are pricy chips (the fab is still being depreciated) but it only lasts one to two years. However, that node can continue for 25 years, in some cases, as with 28nm, with variations such as optical shrinks or process tweaks. The really big challenge is at the beginning of volume manufacutring since a company like Qualcomm ramps a product from zero to high volume essentially instantaneously. That means a product ramps in months, as Qualcomm and Samsung did at 14nm and now 10nm. This scale requires new thinking since the whole supply chain has to cope with the pace and scale of a Qualcomm volume ramp.
It is hard to believe, but the oldest process that even got a mention was 10nm. Earlier processes like 14nm have been in volume manufacturing for years and are mature. 10nm is in volume manufacturing. 8nm will roll out this year. There are all the usual questions about cost, but based purely on technology, the notion that Moore's Law is slowing down is just not true.
I apologize for not being able to give much color, but the facts were presented so fast, one after another. There is actually a huge amount of information in the next couple of dozen lines. Just think how many billion dollars, man-years of R&D, and more is required to make these bullet points a reality.
Some milestones for upcoming processes:
Further forward, 7nm is based on EUV adoption, with a 45% area reduction, 20% speed up, and (presumably and/or) 45% dynamic power reduction compared to 10LPE. Development is on-track with 36nm pitch single exposure. SRAM (256Mb) is at 77% yield. PDK 0.1 will be available in June...wait, it's already June.
6nm will be a smart scaling of 7nm, sharing most 7LPP process, the same SRAM, TR, and BEOL.
5nm will use a second-generation EUV process, focusing more on scalability and power reduction. There will be innovation in MOL and BEOL, too.
4nm is beyond what FinFET can do, and there will need to be a gate all around (GAA) structure. MBCFET (multi-bridge channel) is the most realistic way to secure manufacturability of GAA.
My post tomorrow will go into more detail about both EUV, and the on Wednesday technologies past FinFET.