Samsung Foundry Forum: 10, 8, 7, EUV, 5, 4, GAA, 3...

Last week was the Samsung Foundry Forum. Almost exactly a year ago, Samsung reorganized so that foundry was a standalone business, a part of device solutions (along with memory, and system-LSI). As you might expect, US contributes the most revenue to foundry. There are two new fabs, S3 and S4, in operation, and an EUV lithography line under construction. They passed all their customer audits in the last year, 20 of them, with 9 in automotive. 

If I had to sum up the day's presentations, it was that Samsung have a very ambitious process roadmap, and also put a lot of effort and investment into SAFE, the Samsung Advanced Foundry Ecosystem, to ensure that IP, tools, and flows are available when the processes are available.

Samsung, like other foundries, won't allow us to take any pictures and don't give us any handouts. I have tried to recreate from memory and notes the master process roadmap slide (for FinFET, FD-SOI has its own roadmap). First, a word about naming. Samsung take most processes through several generations through "smart scaling". The first generation of the process has a suffix E (for early). Then P (for perfrormance), then the third generation has C (for cost-reduction), and finally a fourth generation with U (for ultimate). All four versions don't always exist, but that's the decoder ring to understand the process names that this post is flooded with. The business strategy is that the first process is introduced for high-volume mobile customers (that's the E process). Then it is performance enhanced for HPC/networking (that's the P process). Then it is cost-reduced for consumer markets (the C process). Finally, the performance is enhanced again (to the U process). Often, there is also a shrink, to a slightly lower number. Most of the design rules remain unchanged (apart from the shrink factor).

The Master Roadmap and Summary

The left-hand edge of the boxes is roughly when preliminary PDKs should be available. The right-hand side doesn't mean anything (the boxes are just the same size). In particular, the 3nm GAA processes are scheduled for risk production in 2021.

Specialty (some 12" but mostly 8") is expanding from logic to eFlash, power, display driver, CMOS image sensor (CIS), fingerprint sensor, power discrete, and MEMS.

EUV is going into fab S3 in Korea. It will be ready for risk production in the second half of 2018. They have their own EUV mask-debugging infrastructure. Their wafers per day is over 800, on track for 1000 by end of year. They have demonstrated the illuminator at 250W, so they are on track for 1500 wafers per day (in 2020), which is what is the goal for economic volume production. They will initially do EUV production with no pellicle, but they are working on pellicles and will eventually use them (my guess is that they can get away without a pellicle for contact/cut masks, which are mostly dark, but not for lines). Other aspects of EUV such as single line open, and improved photo-resist, are all on track too.

The 5 big fabs are S1, S2 (Austin TX) running 65-14nm, S3 running 10-7nm with a dedicated EUV line. S4 is dedicated to CIS production. There is a lot of assured capacity in place. Currently, 28nm is 30% of capacity. They are adding 28 FD-SOI too. 28nm is the last node before FinFET so is seen as a very, very long-lived node. 14/10nm and 10/7nm are each over 20% of production.

They have a lot of advanced packaging: FOPLP-PoP (fanout PLP) higher performance, thinner, and smaller. I-Cube (2.5D) for four HBM2. 3D SIP (ready in 2019) for homogeneous integration.

Samsung is also looking towards application solutions for HPC-AI to drive the 4th industrial revolution. This combines 7nm and below, ASIC service, Samsung DRAM and 3D NAND, 3D packaging. Because of their extensive memory portfolio, they can be a one-stop-shop. Similarly for connected applications (mobile, automotive, IoT).

They explicitly said that 10/8nm will be a long-lived node, as is 14/11nm (and going way back, 28nm). Note that last year they said that GAA would come at 4nm, but now they have pulled 3nm in and so GAA will come there, and they can extend the lifetime of 4nm with FinFET. 7nm is EUV (there is a 3:1 difference in price so economics mean that single-layer EUV is cheaper than triple patterning but more expensive than double patterning).

FD-SOI was not mentioned in the morning (and does not appear on the roadmap slide above), but was covered later in the afternoon.

The Details

All the above information came from the 40 minute press briefing that we got given before lunch. The foundry forum itself, with a huge audience, was in the afternoon. There was a lot more detail than in the press briefing, and they ran through each process node in turn. When I say "performance a%, power b%" that means you can take the better process to increase performance or to lower power, but not hit both numbers at the same time.

SD Kwon, SVP of the Logic PA Team (device architecture) said that the big innovations come at the big inflection points: 32nm HKMG, 14nm FinFET, 10nm Multi-ArFi, 7nm EUV, 3nm GAA. The way they develop a process is to evolve a mature baseline process with plug-in modules.

Pure pitch scaling (reduce CPP and MxP) on its own is not enough, so smart scaling is also required. At 14nm, they got 8% from that. This covers things like reducing the number of dummy gates, and adding smart diffusion break (SDB). Another is what they call "flexible contact placement" which I believe is what is usually called COAG, contact-over-active-gate. The pictures showed the contact moving from the central area of the cells to where the fins are, anyway. Next is adding mixed diffusion break (MDB) which "breaks the performance limitations of FinFETs". 

Some smart scaling in the roadmap diagram above. From 14 to 11 there is Mx scaling. 8LPP to 8LPU has low power cells with single fins, and Mx scaling with EUV, and MDB. From 7LPE to 5 uses the flexible contact version 1, then down to 1 fine, then to 4LPE with next generation of contact, and Mx scaling. Then to gate-all-around. 

11nm

This is the "one ring to rule them all" technollogy, with the best PPA in the class of 11-16nm processes. Performance 1.07X, area 0.82X, power 0.71X from 14LPP. There is an optional Vt for higher Fmax (+5%). 48nm pitch for m2.

10nm

This is the most advanced high-volume-manufacturing technology, inherited from 14nm.

8nm

The most optimized and economical node. This is the 3rd generation of the 10nm family, reusing all the 10LPP IPs (just scaled). 10% area reduction. 44nm m2 pitch.

8LPU is faster, and has lower power consumtion. With the Fmax boost from uLVT and MDB the performance is close to 7nm, 15% better performance. Power reduction is 0.44X for single fin devices versus 3 fin.

7nm

7nm uses EUV lithography for some layers. It is a very aggressive pitch-scale (presumably due to EUV) with a 46% area reduction (just like the old days), 17% speed up, 48% power reduction from 10nm.

5nm

5LPE is an easy migration from 7LPP. "Smart migration." Performance is 1.05X, power  0.82X, area 0.77x, versus 7nm. Key features are MDB, flexible contact placement (phase 1), and 1-fin device (for power reduction).

4nm

4LPE is further scaling, with extreme scaling of MOL and BEOL. There is flexible contact placement (phase 2), additional cell area shrinkg of 10% enableing M1 27nm/40nm.

3nm

3nm is gate-all-around (GAA). Performance 1.15X to 1.2X, power 0.5X compared to 7nm. Easy migration since, despite the very different transistor architecture, it is mostly a FinFET compatible process. The width of the nanosheets can be varied, like with planar transistors, so this escapes the quantization of FinFET (where you can have 1, 2 or 3 transistors etc but not vary their size). So this means that you can have variable drive (and probably means analog design is more feasible than with FinFET, I presume). The pictures all showed 3 nanosheets per transistor.

FD-SOI

Gitae Jeong, SVP of the LSI PA team talked about "mainstream tehnology". As he said, these technologies consume more wafers than the most advanced technologies (mostly 28nm I'm assuming). But the minastream roadmap then goes to FD-SOI instead of FinFET. The SOI process architecture is especially attractive for RF, and especially millimeter wave for 5G. Their process naming is "FDS" for the FD-SOI processes.

28FDS is on track for high volume manufacture with the first 5G mmwave RF product verified. There are 17 products planned in 2017, and more customers coming all the time. mmwave is up to 100GHz, fmax>400GHz.

28FDS+eMRAM will be available this year, with full manufacturable e-NVM solution. They have successful demos of test chips, 2 major companies engaged, and 10 more under discussion. Industrial temperature range from -40°C to 125°C. 94% yield (8Mb). Solder refloex feasibility achieved. So there are no technical barriers to mass production.

28LPP+eFlash is targeted at IoT (apparently Samsung is the only company with 29nm eFlash memory).

28LPP is a million wafer seller, also with RF and eFlash, ready for security, IoT etc.

28FDS+RF+eMRAM is also working, and is being extended to 18FDS+RF+eMRAM. 18FDS has the same BEOL as 14nm and is the migration path for MCU and IoT applications. PDK will be in September 2018 as planned. Performance is up 22%, power 37-55% down (versus 28). PDK 1.2 with eMRAM will be December 2019. 18FDS metal pitch is 64 using double patterning (28FDS was 90nm single patterned). 

8” Specialty Technology

Samsung is expanding capacity over the next few years. They were at 190K wpm and currently are at 250K wpm, and will go up to 350K wpm. There are increasing numbers of customers with new applications (10 already in 2017).

CMOS Image Sensor (CIS) needs back trench isolation for the future, and a large microlens.

Power IC technology: they have shipped over 1M wafers with a unique device architecture. Automotive grade 1 is available. eFlash option is available with a very small flash macro.

They have two types of fingerprint sensors, one capacitive (built in 180nm) and one optical (built in 90nm), and this can be used to eliminate the home key since it can be on the screen.

Packaging 

Dae-Woo Kim, VP package development team, laid out the packaging roadmap.

The biggest surprise to me was that they have PLP (panel-level package) technology. Instead of using a 12" wafer as the substrate and attaching die to that, it is done the size of big flat-panel displays using equipment that Samsung already uses for display technology. It has a fine pitch RDL and no chip bonding process. There are embedded passives devices in the RDL (such as capacitors and inductors). There also can be a backside RDL too, allowing memory to be stacked on the top. Panels, being rectangular, don't lose die slots near the edge like a circular wafer, plus there is the large panel size. Panel level package is in mass production as of 2Q 2018 (currently just samples). 

The focus of the mobile package roadmap is to enhance i-PoP with 130um interposer in the middle of PoP. FOPLP-PoP is a high performance solution for premium mobie, that is thinner and smallergoing forward. It also can take thicker silicon (despite being thinner) and has better power dissipation than i-PoP.

AI/server/HPC package roadmap is all about big packages. This is 2.5D silicon interposer. There is a complex roadmap that seems to run out to 2023 or 2025, involving lots of HBM. 30um bump pitch with package size over 100mm x 100mm.

They have two different interposer processes, CoS and CoW (chip on substrate, and chip on wafer). They thin die to 100um for COS. But CoW handles the entire wafer without cutting, then attach the devices, mold it, attach to PCB substrate. CoS is cheapest (by about 20%) but its size is limited to 1200mm². If you need four or more HBM then you have to use CoW. 2.5D Si-interposer. Mass production readiness is Q4 2018.

Samsung has advanced packaging that they haven't announced, called Chip Last Mult-Die Fanout Package, that has lower cost and larger size. It is not Si-interposer-based, they are developing a different technology. I didn't quite understand what was being disucssed here, but I think we were getting a sneak preview of something, so we weren't meant to understand it all.

Wafer bonding technology is mature. W2W and CoW bonding have been used for CIS since 2014: grab the sensor wafer, and attach it to the logic wafer. There is package development to go to the next stage and put CIS, logic, and DRAM in the same package, as in the Galaxy 9. They are working on Cu to Cu hybrid bonding for W2W and D2W, and when it is ready they will be able to support a bond pitch of less than 10um.

But his big news was that FOPLP mass production has started, and 2.5D Si-interpower mass production is ready.

Walmart

No, you can't buy Samsung wafers at Walmart. But to break up all that roadmap stuff, Jeremy King, Walmart's CTO came on stage. He didn't have far to come since he works at Walmart labs which are over in Sunnyvale. Did you know Walmart is the largest company in the world, with over 12,000 locations worldwide. Over 140M people walk into a Walmart every week in the US alone. I will just give a few hightlights of his talk since a lot of it was in the form of videos.

One big development (in both the literal and figurative sense) is the Pickup Tower, basically a giant ATM machine. One of the challenges in Walmart is getting people in and out of the store, and this allows you to use your mobile device to pick what you want, then having built an order online, come back and pick it up and be out within 5 minutes. Another part of this is the shelf-scanning robots with a tower of cameras. Since for groceries, the orders are picked off the shelves, it is important that the data is accurate. And Walmart is also the world's largest grocer (and Jeremy didn't say it, but I have read elsewhere that they are the world's largest vendor of organic food, which isn't the first thing you think of when you think of Walmart).

Another challenge is how to make it easy to build an order. When you go to Amazon, you typically buy a couple of things. But a grocery order might have 100 items, and even if it only takes 10 seconds per item, that is a long time.

One thing that he emphasized is scale. Vendors want to put beacons all over the store. You need 50 to 100 per store. But with 4,700 stores in the US, that's a lot of beacons. Plus they remodel 250-500 stores per year, so it is 100Ks of beacons.

All their apps are built on an open stack (some of which they developed and then open sourced), which is something Jeremy introduced when he came on board 7 years ago. Each store has a small 3-rack datacenter, and there are 10 racks in each of 300 distribution centers. However, cloud is now their native culture. It changes everything.

Panel

The day wrapped up with a panel session on the SAFE ecosystem (that's what the "E" stands for). I won't try and recap what all the panelists said. By and large they were all emphasizing the way that Samsung Foundry had partnered with them, and how the whole ecosystem has come together. The panelists were:

• Jaehong Park, Samsung Foundry
• Gus Yeung, Arm
• Babu Mandava, Cadence
• Deirdre Hanford, Synopsys
• Joe Sawicki, Mentor

At the end, the panelists were asked what challenges they see coming in the future, especially with respect to GAA at 3nm. I'll leave a brief summary of what each person said:

Gus: We we need to do DTCO [design technology co-optimization] early. It can’t be lip service. What we see from Samsung is commitment.

Deirdre: DTCO is a really critical partnership model. GAA will require new extraction, new timing models, gigantic designs. There will be impacts on placement and synthesis. This will be tough.

Joe: We end up feeding ourselves with the previous generation of chips. I can guarantee on 3nm side we will be using AI. And thank goodness we say goodbye to quantized gates again.

Babu: Hopefully we can make the cycle of change quicker, availability of tool flow, packaging. We can’t take as long as we took from 16nm to 7nm. The money is in the middle of the pack, we all need that.

Jaehong: Achieving Moore’s law every day is not easy. We need DTCO, DFM, EUV. There are many hurdles as everything gets smaller.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.