Recently, Samsung held the third Samsung Foundry Forum (SFF) at the Marriott in Santa Clara. They had so many attendees that they pretty much overflowed the biggest ballroom in the hotel and had to set up a temporary structure in the parking lot for registration.

As Charlie Bae, EVP of sales and marketing pointed out:

At the first SFF in 2017, there were 250 attendees. Last year there were 500. This year there were 1300 registered. Next year we're going to have to move to a bigger location...maybe Levi Stadium.

As seems to be traditional for foundries, they provide a huge amount of data, but don't hand out any of the slides, and don't allow photography or recording. Samsung even has a special press briefing in the morning, but the same rules apply. So there's probably at least one error in this post!

Big Picture

Samsung foundry use three 300mm fabs:

• S1 in Giheung, Korea
• S2 in Austin, TX
• S3 in Hwaseong, Korea, for 10nm and below, including EUV lithography
• S4 is planned, but Samsung was unable to disclose anything when asked about it in the press event (according to the above chart, it currently is running CMOS image sensors)

They also have one 200mm fab (also in Giheung), which they are expanding aggressively. It had 190Kwpm (thousand wafers per month) in 2017, went to 250Kwpm in 2018, to 277Kwpm in 2020, and will go to 300Kwpm in 2021. This is used for bulk silicon, epi, MCU, small panel, large panel, imaging, logic/analog, RF, power discrete, and more.

Process Roadmap

A couple of times, Samsung presented their process roadmap on a single diagram. I think I have managed to reproduce it accurately above. Here's how you read it. Across the top in blue are the main process nodes. The brown boxes below are derivative processes, if they have red arrows then they are an optimization, if they have pink arrows, they are adding additional modules.

The really big transition is the last one since it has a new transistor architecture that Samsung calls MBCFET (which stands for Multi-Bridge-Channel FET). This is their 3nm gate-all-around (GAA) nanosheet transistor. I'll cover that in more detail in its own post.

Note that Samsung has other processes, in particular, they have FD-SOI in addition to the FinFET processes above (which they call 28FDS and 18FDS). They also have some specialty processes that they run in their 8" fab.

Some highlights:

• 7nm has been in mass production since April with EUV
• 6nm from 2H 2019
• 5nm process development was complete in April, mass production in 2H 2020, first tapeout in 2H 2019, mass production starts 1H 2020
• 4nm process development will be complete in 2H 2019
• 3nm GAA PDK 0.1 released

One problem that all foundries face is that embedded flash runs out of road at 28nm. Dedicated flash memory has gone vertical to cope with the inability to scale further, but that doesn't work for flash embedded in logic for obvious cost reasons. Samsung has gone the eMRAM route (embedded magnetoresistive RAM). This is a memory that is built entirely in the BEOL (so in the interconnect stack), which means it can be added relatively easily to any FEOL. Since Samsung have FD-SOI, that is where they are focused on adding RF (it works better on an insulator). The current roadmap is:

• 28LPP + eFlash + RF
• 28FDS + eMRAM
• 18FDS + RF + eMRAM
• FinFET + eMRAM

The first 28FDS eMRAM product was shipped in March 2019. There is a 1Gb eMRAM development that is on-track. eMRAM on FinFET is under development at 14nm, 10nm, and 7nm.

For 5G, Samsungs's roadmap is to use as base processes:

• Sub 6GHz, 14LPP in production with 8LPP available in Q3
• mmWave: 28FDS in production, with 18FDS/8LPP available in Q3

Samsung went all in on EUV at 7nm (and below), without having a 193i multi-patterned version of the process as a fallback. In the press presentation, they were asked how many critical layers there were where EUV was used, but they said that the weren't allowed to say. However, they did let on that 6nm and 7nm it is "high single digit", 5nm is "a little bit more", and 4nm "some additional layers."

As to the 3nm GAA process, 3GAE is risk production in late 2020, 3GAP is risk production in 2021, volume production is 2022. A few more quotes from the press event:

I think GAA will introduce a new era in our foundry business.

Even though GAA provides better electrical than FinFET, a lot of it is compatible with the FinFET process, especially BEOL.

Samsung is the only company offering GAA technology in the world.

Packaging

Samsung presented a roadmap for advanced packaging, focused on two areas: mobile and HPC/AI. The reason for two roadmaps is mainly driven by bandwidth. For the server side, this can be 1-2TB/s, but mobile only requires 100GB/s.

Mobile: They introduced PoP about eight years ago, with 50GB/s. Then FO-PKG with bandwidth of 100GB/s which is both thinner and cooler. In the future there will be FO-SiP (with die side by side) at over 200GB/s. They are using panel-level package (PLP) technology. This leverages Samsung's manufacturing capability for large displays/TVs. They have B-RDL (backside RDL) for memory integration, and RDL for fine pitch, with embedded passive devices. Rectangular panels give much better utilization than a 300mm wafer where about 15% of the area is lost around the edge. Mass production started last July. There is also the capability for antenna-in-package (AiP) with patch and dipole antennas for vertical and horizontal radiation.

Server: They have introduced HPC/AI/Server platform with two directions: large package using 2.5D silicon interposer (CoS), smaller package using multi-De 3D with high-bandwidth memory (HBM) at 50um routing pitch, 3D SiP (chip-on-wafer) at 30um, and 3D SiP (D2W) at about 10nm.

The summary sentence is FOPLP mass production is in progress with first backside RDL. 2.5D CoS technology is ready for manufacturing.

SAFE

Safe is Samsung Advanced Foundry Ecosystem.

In EDA, there are 16 partners (of which one is Cadence, of course) with 50 tools. That morning Cadence announced the certification of the custom/AMS flow on 28FDS.

IP has 27 partners (Cadence again being one) with 1500 IP blocks available.

New for 2019 are:

• GDDR6 and HBM2e IP for HPC/AI
• 56G and 112G long reach SerDes, 40G die to die SerDes
• 4/3nm IP development

That morning Cadence announced several test chip tapeouts with Samsung:

• DDR5/4 on Samsung 7LPP
• GDDR6 on 14LPP
• 2.4G HBM2 on 10LPP and 8LPP
• 112G long-reach SerDes

Also, Cadence's GDDR6 IP has achieved silicon success on 7LPP.

GAA

I'll cover the 3nm GAA details in a separate post next week.

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