Get email delivery of the Cadence blog featured here
At DesignCon at the end of January, a team from Cadence presented to a standing-room-only crown on Modeling and Simulating 112Gbps SerDes. The team was Margaret Johnston, Manuel Juschas, Bhaskar Acharya, Kumar Keshavan, and Ken Willis. The 112Gbps SerDes they were discussing was the one I talked about when we announced it in my October post The World's First Working 7nm 112G Long Reach SerDes Silicon.
Traditionally, SerDes schemes have used NRZ signaling. This is stands for Non-Return-to-Zero. It is a fancy way of saying that the 1-bits are transmitted as a high voltage and the 0-bits as a low voltage. There are other signaling schemes, such as Manchester encoding, where a 0-bit is transmitted as a low voltage for half a bit, followed by a high voltage for half a bit (and 1-bits are transmitted with the two half bits the other way around). The original DIX Ethernet used Manchester encoding.
One challenge with NRZ encoding is that a long sequence of the same bit (such as all zeros) has no transitions at all. Since there is no separate clock, it becomes impossible to recover the clock, and thus accurately recover the data. The Manchester scheme I mentioned avoids this since there is a transition in the middle of every bit. On the other hand, it is wasteful of bandwidth, using twice as much bandwidth as NRZ. The long sequence problem is solved at a higher level by ensuring that sequences like that never occur. There are a number of ways to do this, one is known as bit-stuffing. If a sequence of (say) 5 0-bits or 5 1-bits occurs, then the other bit is inserted to ensure a transition. At the receiver, if such a sequence of 5 bits is received, the following bit is ignored (de-stuffing). Obviously, this uses up a little of the bandwidth of the channel, but it makes the signal self-clocking by guaranteeing a transition at least every 5 bits.
An NRZ SerDes will show the traditional eye-diagrams, such as in this picture (which is a Cadence 16Gbps SerDes that we showed at DesignCon three years ago):
To get a data rate as high as 112Gbps is impossible with only one bit transmitted at a time. Instead, PAM-4 signaling is used. This stands for Pulse-Amplitude-Modulation and the 4 indicates that there are four different voltage levels used (there is also a PAM-3 that is less commonly used). The picture below shows the 112Gbps eye diagram on the scope. The 4 levels mean that there are three eyes, and they are clearly visible:
Just to add to the confusion, there are multiple naming conventions for the four levels:
Another wrinkle is that the symbols are normally Gray coded. Gray coding was originally invented for preventing spurious errors from rotational encoders and mechanical switches. It has the attribute that only a single bit changes between successive values, as opposed to normal binary coding (sometimes called linear) where, for example, 4 bits change between 7 and 8 (when 0111 goes to 1000). With mechanical switches, for example, there is a possibility that some bits transition slower than others, leaving a spurious value (for example if 0111 changes to 1111 on the way to 1000). Gray coding in the SerDes context means that the 4 values (from lowest to highest voltage) represent 00, 01, 11, 10. This means that if the voltage is "off by one level" then only a single bit error occurs in the datastream. With linear coding, if a mistake is made distinguishing between the middle two voltages (between 01 and 10) then both bits are wrong.
The picture above shows the test chip for the Magpie 112 Gbps SerDes IP. It was manufactured in 7nm technology. It has multi-rate support, with 112/56Gbps PAM4 signaling, and also 56/28/10Gbps NRZ for backward compatibility. I took the picture above on our booth at this year's DesignCon. If you want to use it in a design, it is available now.
The diagram to the right shows the eye height for both NRZ and PAM-4. The eye height is obviously ⅓ the size of that for NRZ, which reduces noise margins (by about 9.5dB). Note that the three eyes are not symmetrical—in particular, the middle eye is a different shape from the top and bottom eyes. Transitions between non-adjacent levels take more time than transitions between adjacent levels, which increases jitter.
For general information on SerDes equalization, see my post about the tutorial that Cadence and IBM presented on the first day DesignCon: Cadence Teaches AMI and IBIS. Specifically for the Magpie SerDes, the transmitter equalization is DAC-based with 4 taps of transmitter equalization (in the lower half of the diagram below). The receiver is DSP-based with both FFE and DFE. The IP is fully autonomous at startup, initializing the DFE to adapt to the environmental conditions using pseudo-random bit sequences.
To build a working system, two SoCs (or perhaps two instances of the same SoC) are involved. To handle the analysis of package, board traces, and so on, IBIS and AMI are required (again, see the tutorial linked above if that is gobbledygook to you). We had to enhance multiple AMI modules to handle the multi-level PAM4 signaling:
FFE (feed forward equalization) is traditionally only used in the transmitter for NRZ signaling. But with PAM4 it can also appear in the receiver.
The purpose of all this analysis has several aims, such as ensuring that the eyes are open and then calculating a bit error rate. Ultimately, this all depends on having a good correlation between silicon and the analysis performed by Sigrity.
First the transmitter (silicon vs simulation):
And the receiver. The bit-error-rate (BER) is 3e-06 in both silicon lab testing (on the left) and Sigrity's SystemSI simulation (on the right):
So this shows that we successfully modeled the Magpie SerDes equalization with Sigrity SystemSI technology and the AMI builder, and correlated the initial silicon with simulations. In other words, it all worked.
To see my post about the SerDes when we announced it (the same one referenced above), see The World's First Working 7nm 112G Long Reach SerDes Silicon. If video is your thing, then watch Wendy Wu explain How the Cadence 112G SerDes IP Solves the Challenges of Long-Reach Signaling. Or just watch it here:
For information on the 112G SerDes itself, see the product page.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.