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Here's a nightmare. You sign off your design with the usual margins. It is a 7nm chip that is meant to run at 3GHz. But it only runs at 2.7GHz. You get Cadence to help you work out what is going on. It turns out that it is due to a critical path in your design. It didn't seem like it was a critical path. When you did timing analysis, it had a positive slack of 50ps. It was about the 200,000th most critical path. But analysis had not been done with Tempus Power Integrity, and when it was run, it identified that the actual slack was negative 62ps due to IR drop. It wasn't the 200,000th most critical path, it was the top of the charts.
What gives Tempus Power Integrity its edge? It is that Tempus Power Integrity is an integration of the Tempus and Voltus solutions. In fact, here's something you might not know, or even guess. While Tempus and Voltus are separate products, they have always been the same binary. They are truly integrated under the hood.
Another great attribute of the Tempus and Voltus systems is that they can take advantage of running in Cadence Cloud, like many (most) tools in our portfolio. If you are a huge company with many designs in flight at the same time, you can keep a huge server farm and a large number of licenses busy 24/7. The cloud is maybe a nice-to-have addition.
However, if you are a smaller company with only one or two designs, you have a different issue. You don't want to provision your compute infrastructure for your peak load, and you probably can't afford to anyway. You also don't want all those signoff licenses when you are not signing-off anything. Cadence Cloud is perfect for this. It allows your compute infrastructure to be at a normal level for most of the project, and then at the end when you have peak loads for physical design and signoff, you can expand to many more machines and licenses.
But those big companies love it, too. Over half of the top 25 semiconductor companies use Tempus Signoff, and over 80% of the top 25 semiconductor companies use Tempus ECO.
Thanks to tight integration, the Innovus + Tempus ECO flow delivers the best PPA in half of the time. But don't listen to me, let a customer talk about it:
The way it works is that you run sign-off timing from Innovus, and give it options to recover the timing:
1. Innovus sends the design to Tempus to time it (from
the Innovus cockpit)
2. Innovus brings back the ECOs that Tempus suggests
3. Innovus implements the ECOS and then reroutes the design
4. Innovus sends the revised design to Tempus to time it
to make sure it met the spec.
You can do this multiple times if needed, and never have to run/call
Tempus separately. The two tools have a handshake between them, so
for ECOs you don't have to lift a finger.
I have no idea who that customer is. Here's another one:
Our Tempus/Innovus STA + ECO cycle can be done in 24 hours or less.
These came from John Cooley's DeepChip site, where Tempus fast ECOs, signoff, and MMMC is Best of EDA #8b. If 8th seems pretty far down the list, let me point out that we just have too many great products. In Cooley's list for last year, first equal were two Cadence products, Palladium and Protium. Second equal was Spectre X. And fourth was Clarity 3D Analysis.
Here are a couple of videos that look at Tempus Power Integrity Signoff. First Cadence CVP of engineering for the electrical signoff product line, Michael Jackson, on Achieving Superior Design Convergence with Tempus Power Integrity (2½ minutes long):
And second, Maxlinear's Sarathy Gopal on Maxlinear Signing-Off Using Tempus with Confidence for FinFET Designs (4 minutes):
These are the product pages for the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution. Or you can look at the page I referred to on DeepChip.
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