This morning at DAC, Cadence announced the Spectre X Simulator, the latest version of its circuit simulation product. The short value proposition is up to 10X speed improvement, up to 5X capacity improvement, the same golden accuracy. So the same results as the old Spectre simulator, but faster, and on bigger designs.

The Spectre X simulator allows massive parallelization of long simulation runs across up to 128 CPU cores, and across multiple machines. It can also be run in Cadence Cloud. Spectre X supports the same industry-certified device models and syntax. For mixed-signal verification, it is tightly integrated with the Xcelium Parallel Logic Simulator.

Two big challenges facing analog simulation are the increasing process-node complexity, and the increasing complexity of analog designs.

Process-node complexity includes the complex parasitics of FinFET and GAA transistors, the need for more corners and more process variation, and the lack of passive elements or precision transistors (due to quantization of FinFET designs, although GAA promises some relief in this area). Analog design has changed over the last decade and is increasingly mixed signal, with a portion of comparatively low-precision analog and then digital signal processing techniques used to calibrate and correct for the lack of precision. For example, modern SerDes designs are all done this way. There are also new levels of integration involving technologies such as MEMS, sensors, and silicon photonics. Approaches to cope with this have historically been to sacrifice accuracy and use FastSpice, or to approximate the behavior with SystemVerilog models.

The Spectre X simulator addresses this by improving the speed without compromising accuracy, making these historical approaches that cut corners unnecessary. It can simply be dropped in anywhere Spectre is used today, including full support of the Virtuoso ADE, Virtuoso RF, Liberate, and Legato solutions, which all automatically benefit immediately from the speedup.

Under the hood, there are new numerical analysis methods that allow the simulator to more intelligently solve much larger circuit equations without any loss of accuracy. New optimized modeling methods for devices and interconnect combined with overall data model improvements provide efficient handling of the largest pre- and post-layout designs. The capability to distribute simulations across multiple CPUs leverages modern multi-core architectures and massively parallel simulation in data centers and the cloud.

That leads to speedups as in the above chart, which compares Spectre X runtimes (in green) to Spectre APS runtimes (in orange). These designs are a power management IC, a phase-locked-loop, SerDes, an ADC, flash memory, and a CMOS image sensor.

The above graph shows the speedup as the simulation of a CIS (150K transistors and 45M parasitics) is distributed across more and more cores. With the maximum 128 cores the speedup is 30X compared to the doing the simulation on a single core, bringing the simulation time down from nearly two days to an hour and a half.

Early users of the Spectre X simulator include MediaTek, Mellanox, Renasas, and Silicon Works. Ching San Wu, the General Manager of Analog Design and Circuit Technology for MediaTek detailed their experience:

We have simulated our advanced-node 5G designs with the Spectre X simulator and it shows up to 7X run-time improvement, even when factoring in large amounts of parasitics in post-layout verification.

More Information

For more information, see the Spectre X product page.

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