DAC...and the State of the RISC-V Union

Due to the pandemic, events that normally occur earlier in the year all piled up in December. The Design Automation Conference, SEMICON West, and the RISC-V Summit all took place in the second week of December, with the International Electron Devices Meeting (IEDM) taking place the following week (its normal time). All in San Francisco.

I went along to DAC and RISC-V and attended the SEMI press lunch which I already wrote about in my post The Outlook for Semiconductors...Especially in Cars. I also covered Joe Costello's keynote at DAC in my post Costello's DAC Keynote. This (or rather these, since there were 3 events) was the first in-person event I've attended since the RSAC security conference in March 2020. Actually, I did attend DVCon the following week, but only for about 30 minutes before Cadence decided to pull all employees out. It is amazing to think that it is coming up towards two years since that happened. You can see one change on the picture of my badges at the head of this post: those green stickers indicate that I proved I was vaccinated. SEMI was meant to be set up so you couldn't get your badge without proving your vaccination status, and then you could come and go through other doors, but something got messed up so you had to prove you were vaccinated every time you entered the Moscone Center. They wouldn't even accept the green stickers, "that's Moscone West, nothing to do with us". In Britain we call people like that a jobsworth—"if it were up to me I'd let you in but it's more than my job's worth, so no".

As I said, DAC was in-person. Apparently, there were about 1,000 people registered for the conference compared to over 5,000 in the before-times. That's a low number but not really surprising given that this is one of the first in-person conferences that has taken place. Even some of the exhibitors had clearly dropped out at the last minute leaving a sign saying they would see us all in 2022.

That is a good segue into me giving you the save-the-date information. DAC 2022 will be July 10th to 14th, co-located with SEMICON West as is now the new normal. Both RISC-V and IEDM have traditionally been in December so I assume they will continue, although I've not seen any dates.

DAC 2021 is available until January 1st as a virtual on-demand program (but you have to be registered).

RISC-V

One great thing about RISC-V is that RISC-V International (based in Switzerland these days) is that it puts everything up on the web. Every presentation from the recent RISC-V Summit is on YouTube, and not on some weird platform where it is hard to find anything and you've probably already forgotten your password. You don't even need to register for the event to view the videos. The event was in-person, so there were plenty of good reasons to attend the actual event. And the videos were only posted to YouTube the following week. Here's The RISC-V international YouTube channel for your viewing pleasure.

I'm not going to pretend that I've watched all these videos. But let me summarize a few presentations:

• Calista Redmond, CEO of RISC-V International: Welcome and Opening Remarks.
• Krste Asanović, who led the original RISC-V project and is both a professor at UC Berkeley and Chief Architect of SiFive, The State of the RISC-V Union.
• Calista Redmond (again) Where Is RISC-V Going?

The second two of the three will be covered in a subsequent post tomorrow.

Calista

One of the things that RISC-V gets criticized for is that it has a lot of traction in academia, and various cores announced in industry. But where are the actual shipping chips and products? Well, in 2021 there were 2 billion RISC-V cores shipped. In one way, that is impressive, but "cores" might be a bit of statistical shenanigans. A single Esperanto chip contains a thousand cores, for example (see my post HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions).  There is a big difference in the multi-core era between a billion chips containing RISC-V cores, and a billion cores. But people who live in glass houses...we at Cadence talk about how many Tensilica cores we have shipped—7B per year. Deloitte predicts that the RISC-V market will double in 2022, so 4 billion cores.

Some statistics about RISC-V that Calista showed. Membership of RISC-V International grew 130% in 2021 to 2,400 members, a similar growth rate to 2020. The whole standardization process got streamlined and 16 specifications got finalized due to what Krste last year called "prioritize and finish things". It launched RISC-V online courses with 8,842 enrollments in the first 9 months (the fastest-growing course the Linux Foundation has ever seen). There were 90 RISC-V events including RISC-V World Conference in China with 1,300 in-person attendees and 20,000 online, the biggest RISC-V event ever.

People are showing up!

She wrapped up with a rallying cry:

This is the open era of computing. Thank you for engaging, collaborating, and commercializing. This is our time.

Videos

Here is Calista's presentations (around 15 minutes).

Calista:

 

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