System in Package

At DAC, Dick James gave a fascinating presentation on system in package, or SiP, at the DAC pavilion. In fact, as a general statement, I have to say that the standard of presentations at the pavilion was very high, and others obviously agreed since many presentations had every seat filled and a ring of people standing, too. Dick used to work for Chipworks but he moved on and now works some of the time with TechSearch International. I know they sound like they should be headhunters, but they actually are specialists in the advanced packaging market.

So what is an SiP? It is two or more dissimilar dies assembled in the same package. The dies can be very different, including MEMS, sensors, antennas, and passives, as well as the more obvious digital, analog, and memory dies. The one thing that is excluded is putting a single die in a package—even an SoC in a package doesn't count as a SiP. That's a bit contradictory, I know, but it is in keeping with Pierre Paulin's adage that "a system is one level above whatever level you are working at".

There are many drivers for SiP but the main ones are:

• Heterogeneity: The ability to integrate die from different processes into a single component
• Size: An SiP is a lot smaller than the same system where each die is in its own package
• BOM cost reduction: Simplified board, lower layer count, reduced design cost (even though the SiP may not itself be cheaper)

There are many formats for SiP, ranging from silicon interposers and die with thru-silicon-vias (TSVs) at the high end, to BGAs with wire-bonded die at the lower end (like the Ax chips in older generation iPhones). In the past, SiPs were a bit limited by a paradox: if SiPs were cheaper, more people would use them, but without the learning from volume, costs remained high. But mobile devices ship in such high volume, hundreds of millions, that they can change that tradeoff overnight.

Another driver is the internet of things (IoT). Almost any IoT device contains sensors, some sort of computation, a communication device, normally wireless, and perhaps some memory. These are impossible to manufacture in the same process and thus on the same die, so it is much more attractive to do the integration at the SiP level. Two big drivers for IoT are the decreasing cost of sensors, and the low cost of multi-die packages and modules. Volumes feed on SiP costs, and SiP costs feed on volume.

Examples of SiPs

This Texas Instruments MicroSiP is a power supply platform. It is just 2.9mm x 2.3mm x 1mm, and that includes the inductor that is mounted on top to reduce board space.

Microsemi have embedded the die in the substrate and reduced the area by 400% compared to the previous version. It is very high reliability, qualified to MIL standard for implantable devices. This approach is also applicable to other high-reliability environments such as aerospace, automotive, and industrial sensing.There is an evolution exemplified here by moving toward ultra-thin embedded die with a lamination thickness of 0.5mm, and an overall module height of about 1mm (which is the limit for discrete components).

FOWLP

Fan-out wafer-level packaging (FOWLP) is characterized by the lack of substrate. A quick summary is that the wafers are sawn, the die are picked and placed on a dummy "wafer" (or perhaps something larger, "panel processing"). The copper redistribution layer is added, and solder balls, and the package molding compound is added. Some mobile chips are using this approach, typically with just a single die, so not technically an SiP, and the volumes are driving the learning curve. It is expected that subsequent generations will include multiple die in the packages.

These can be very thin (<0.5mm) and with extremely high signal density. Current line/space are 10/10um with roadmaps to <5/5um and even 2/2um. The drivers apart from communications are integrating radar modules for automotive applications, and very high-performance HPC designs.

Apple Watch SiP

The state of the art is the Apple Watch. This is a 26mm x 28mm package containing many components. The severe size constraint of a watch means that building this system without using SiP technology would simply be impossible. This picture shows the board, just to give an idea of how dense the design is at that level:

But X-ray analysis by Dick's former employer Chipworks shows that the S1 "chip" is actually an SiP containing about 30 ICs, plus many passives, plus an ST accelerometer/gyroscope included outside the package itself.

AMD's Fiji

AMD's graphics processor uses as a silicon interposer with TSVs. It has a 595mm2 ASIC mounted in the center of the 1.011mm2 interposer, surrounded by four stacks of HBM (each of which consists of a logic die with four DRAM dies stacked on top). There are more than 200,000 interconnects including Cu pillar ubumps and C4 bumps. The interposer has 65,000 TSVs with 10um diameter TSVs.

Sony Image Sensor

You probably already know that the state of the art in CMOS image sensors (CIS) is not to expose the front of the image sensor to the light, as used to be done, but rather thin the image sensor so that it is transparent to the light, then flip it over onto the image sensor processor (ISP) chip underneath, thus not requiring any TSVs. The light to the sensor passes through the back of the thinned die.

Sony have gone one further with a three-layer stack. On the top is the image sensor, and in the middle is a DRAM layer, and the ISP on the bottom. The signals from the image sensor actually pass straight through the DRAM layer to get to the processor, and then back up to the memory. This is the first commercial three-layer stack using wafer bonding. It is actually in a high-end phone, the Sony Experia XZ, launched at MWC in February. The image sensor and the DRAM are thinned to 2.6um! When I started in the semiconductor business, that was the size of a transistor.

Sony are the leaders in image sensors, and are in most high-end phones including iPhone. Dick expects to see something similar to this design in the iPhone 8 (or whatever number Apple gives its next model expected in the fall). This one is capable of 960fps, which is also pretty amazing.

Nokia SP4 Service Router SiP

Hot off the press, only announced a week before DAC, is this Nokia SiP. It is for enterprise routers and so is not in a very cost-sensitive market like mobile. It can process 100TB/s or more. There are 22 chips inside including custom memory. The whole router is the size of a gaming console, which is incredible when you think how many video streams (Netflix, YouTube, etc.) it can process simultaneously.

Summary

This is an area in a state of flux, with the technologies and economics evolving. One big area is whether FOWLP technology will be done by the foundry or by the OSAT, with everyone gearing up for a fight.

SiP is an enabler for many products especially:

• Mobile, tablets, laptops
• SSDs
• IoT devices
• Automotive safety systems, including radar
• Medical wearables
• HPC systems

The main drivers are performance and form factor. But demand for lower-cost solutions drives adoption of new package designs, without a single winner. Economics and business decisions are a big driver, and sometimes technical performance considerations (such as 70GHz radar).

As Moore's Law slows and the most advanced processes are not really suitable for a lot of analog or RF design, SiP is going to become one of the integration approaches of choice, a key aspect of "More than Moore", driving integration higher without depending solely on area scaling of the semiconductor process.